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ASoC: codec: wm9860: Refactor PLL out freq search
Add a separate function for deriving (sysclk, lrclk, bclk) when the clock is auto or pll. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -672,10 +672,70 @@ int wm8960_configure_sysclk(struct wm8960_priv *wm8960, int mclk,
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return *bclk_idx;
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}
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/**
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* wm8960_configure_pll - checks if there is a PLL out frequency available
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* The PLL out frequency must be chosen such that:
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* - sysclk = lrclk * dac_divs
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* - freq_out = sysclk * sysclk_divs
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* - 10 * sysclk = bclk * bclk_divs
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*
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* @codec: codec structure
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* @freq_in: input frequency used to derive freq out via PLL
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* @sysclk_idx: sysclk_divs index for found sysclk
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* @dac_idx: dac_divs index for found lrclk
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* @bclk_idx: bclk_divs index for found bclk
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*
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* Returns:
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* -1, in case no PLL frequency out available was found
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* >=0, in case we could derive bclk, lrclk, sysclk from PLL out using
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* (@sysclk_idx, @dac_idx, @bclk_idx) dividers
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*/
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static
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int wm8960_configure_pll(struct snd_soc_codec *codec, int freq_in,
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int *sysclk_idx, int *dac_idx, int *bclk_idx)
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{
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struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
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int sysclk, bclk, lrclk, freq_out;
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int diff, best_freq_out;
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int i, j, k;
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bclk = wm8960->bclk;
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lrclk = wm8960->lrclk;
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*bclk_idx = -1;
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for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
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if (sysclk_divs[i] == -1)
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continue;
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for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
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sysclk = lrclk * dac_divs[j];
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freq_out = sysclk * sysclk_divs[i];
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for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
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if (!is_pll_freq_available(freq_in, freq_out))
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continue;
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diff = sysclk - bclk * bclk_divs[k] / 10;
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if (diff == 0) {
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*sysclk_idx = i;
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*dac_idx = j;
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*bclk_idx = k;
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best_freq_out = freq_out;
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break;
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}
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}
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}
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}
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if (*bclk_idx != -1)
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wm8960_set_pll(codec, freq_in, best_freq_out);
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return *bclk_idx;
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}
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static int wm8960_configure_clocking(struct snd_soc_codec *codec)
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{
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struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
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int sysclk, bclk, lrclk, freq_out, freq_in;
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int freq_out, freq_in;
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u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
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int i, j, k;
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int ret;
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@ -692,8 +752,6 @@ static int wm8960_configure_clocking(struct snd_soc_codec *codec)
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}
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freq_in = wm8960->freq_in;
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bclk = wm8960->bclk;
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lrclk = wm8960->lrclk;
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/*
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* If it's sysclk auto mode, check if the MCLK can provide sysclk or
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* not. If MCLK can provide sysclk, using MCLK to provide sysclk
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@ -720,33 +778,10 @@ static int wm8960_configure_clocking(struct snd_soc_codec *codec)
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return -EINVAL;
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}
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}
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/* get a available pll out frequency and set pll */
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for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
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if (sysclk_divs[i] == -1)
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continue;
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for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
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sysclk = lrclk * dac_divs[j];
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freq_out = sysclk * sysclk_divs[i];
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for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
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if (sysclk == bclk * bclk_divs[k] / 10 &&
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is_pll_freq_available(freq_in, freq_out)) {
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wm8960_set_pll(codec,
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freq_in, freq_out);
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break;
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} else {
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continue;
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}
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}
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if (k != ARRAY_SIZE(bclk_divs))
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break;
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}
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if (j != ARRAY_SIZE(dac_divs))
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break;
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}
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if (i == ARRAY_SIZE(sysclk_divs)) {
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dev_err(codec->dev, "failed to configure clock\n");
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ret = wm8960_configure_pll(codec, freq_in, &i, &j, &k);
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if (ret < 0) {
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dev_err(codec->dev, "failed to configure clock via PLL\n");
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return -EINVAL;
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}
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