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pxa3xx_nand: remove hardcode register address
Although nand controller is same between PXA3xx and MMP, the register space is different. Remove the hardcode register address setting in pxa3xx_nand.h. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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@ -85,10 +85,6 @@
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#define NDCB0_CMD1_MASK (0xff)
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#define NDCB0_ADDR_CYC_SHIFT (16)
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/* dma-able I/O address for the NAND data and commands */
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#define NDCB0_DMA_ADDR (0x43100048)
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#define NDDB_DMA_ADDR (0x43100040)
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/* macros for registers read/write */
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#define nand_writel(info, off, val) \
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__raw_writel((val), (info)->mmio_base + (off))
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@ -124,6 +120,7 @@ struct pxa3xx_nand_info {
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struct clk *clk;
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void __iomem *mmio_base;
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unsigned long mmio_phys;
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unsigned int buf_start;
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unsigned int buf_count;
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@ -524,11 +521,11 @@ static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
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if (dir_out) {
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desc->dsadr = info->data_buff_phys;
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desc->dtadr = NDDB_DMA_ADDR;
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desc->dtadr = info->mmio_phys + NDDB;
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desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
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} else {
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desc->dtadr = info->data_buff_phys;
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desc->dsadr = NDDB_DMA_ADDR;
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desc->dsadr = info->mmio_phys + NDDB;
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desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
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}
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@ -1241,6 +1238,7 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
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ret = -ENODEV;
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goto fail_free_res;
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}
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info->mmio_phys = r->start;
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ret = pxa3xx_nand_init_buff(info);
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if (ret)
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