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[PATCH] forcedeth: fix initialization
This patch fixes the nic initialization. If the nic was in low power mode, it brings it back to normal power. Also, it utilizes a new hardware reset during the init. I am resending based on feedback, I corrected the register size mapping and delay after posted write. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ayaz Abdulla
Jeff Garzik
parent
bdf9c27d02
commit
86a0f04387
@ -105,6 +105,7 @@
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* 0.50: 20 Jan 2006: Add 8021pq tagging support.
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* 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
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* 0.52: 20 Jan 2006: Add MSI/MSIX support.
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* 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -116,7 +117,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.52"
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#define FORCEDETH_VERSION "0.53"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -160,6 +161,7 @@
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#define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
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#define DEV_HAS_MSI 0x0040 /* device supports MSI */
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#define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
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#define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
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enum {
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NvRegIrqStatus = 0x000,
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@ -203,6 +205,8 @@ enum {
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#define NVREG_MISC1_HD 0x02
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#define NVREG_MISC1_FORCE 0x3b0f3c
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NvRegMacReset = 0x3c,
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#define NVREG_MAC_RESET_ASSERT 0x0F3
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NvRegTransmitterControl = 0x084,
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#define NVREG_XMITCTL_START 0x01
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NvRegTransmitterStatus = 0x088,
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@ -326,6 +330,10 @@ enum {
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NvRegMSIXMap0 = 0x3e0,
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NvRegMSIXMap1 = 0x3e4,
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NvRegMSIXIrqStatus = 0x3f0,
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NvRegPowerState2 = 0x600,
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#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
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#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
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};
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/* Big endian: should work, but is untested */
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@ -414,7 +422,8 @@ typedef union _ring_type {
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#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
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/* Miscelaneous hardware related defines: */
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#define NV_PCI_REGSZ 0x270
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#define NV_PCI_REGSZ_VER1 0x270
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#define NV_PCI_REGSZ_VER2 0x604
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/* various timeout delays: all in usec */
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#define NV_TXRX_RESET_DELAY 4
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@ -431,6 +440,7 @@ typedef union _ring_type {
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#define NV_MIIBUSY_DELAY 50
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#define NV_MIIPHY_DELAY 10
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#define NV_MIIPHY_DELAYMAX 10000
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#define NV_MAC_RESET_DELAY 64
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#define NV_WAKEUPPATTERNS 5
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#define NV_WAKEUPMASKENTRIES 4
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@ -552,6 +562,8 @@ struct fe_priv {
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u32 desc_ver;
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u32 txrxctl_bits;
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u32 vlanctl_bits;
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u32 driver_data;
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u32 register_size;
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void __iomem *base;
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@ -919,6 +931,24 @@ static void nv_txrx_reset(struct net_device *dev)
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pci_push(base);
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}
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static void nv_mac_reset(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
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writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
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pci_push(base);
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writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
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pci_push(base);
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udelay(NV_MAC_RESET_DELAY);
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writel(0, base + NvRegMacReset);
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pci_push(base);
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udelay(NV_MAC_RESET_DELAY);
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writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
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pci_push(base);
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}
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/*
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* nv_get_stats: dev->get_stats function
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* Get latest stats value from the nic.
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@ -1331,7 +1361,7 @@ static void nv_tx_timeout(struct net_device *dev)
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dev->name, (unsigned long)np->ring_addr,
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np->next_tx, np->nic_tx);
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printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
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for (i=0;i<0x400;i+= 32) {
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for (i=0;i<=np->register_size;i+= 32) {
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printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
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i,
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readl(base + i + 0), readl(base + i + 4),
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@ -2488,11 +2518,11 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
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}
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#define FORCEDETH_REGS_VER 1
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#define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
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static int nv_get_regs_len(struct net_device *dev)
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{
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return FORCEDETH_REGS_SIZE;
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struct fe_priv *np = netdev_priv(dev);
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return np->register_size;
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}
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static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
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@ -2504,7 +2534,7 @@ static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void
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regs->version = FORCEDETH_REGS_VER;
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spin_lock_irq(&np->lock);
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for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
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for (i = 0;i <= np->register_size/sizeof(u32); i++)
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rbuf[i] = readl(base + i*sizeof(u32));
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spin_unlock_irq(&np->lock);
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}
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@ -2608,6 +2638,8 @@ static int nv_open(struct net_device *dev)
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dprintk(KERN_DEBUG "nv_open: begin\n");
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/* 1) erase previous misconfiguration */
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if (np->driver_data & DEV_HAS_POWER_CNTRL)
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nv_mac_reset(dev);
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/* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
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writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
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writel(0, base + NvRegMulticastAddrB);
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@ -2878,6 +2910,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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unsigned long addr;
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u8 __iomem *base;
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int err, i;
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u32 powerstate;
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dev = alloc_etherdev(sizeof(struct fe_priv));
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err = -ENOMEM;
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@ -2910,6 +2943,11 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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if (err < 0)
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goto out_disable;
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if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL))
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np->register_size = NV_PCI_REGSZ_VER2;
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else
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np->register_size = NV_PCI_REGSZ_VER1;
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err = -EINVAL;
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addr = 0;
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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@ -2918,7 +2956,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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pci_resource_len(pci_dev, i),
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pci_resource_flags(pci_dev, i));
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if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
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pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
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pci_resource_len(pci_dev, i) >= np->register_size) {
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addr = pci_resource_start(pci_dev, i);
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break;
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}
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@ -2929,6 +2967,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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goto out_relreg;
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}
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/* copy of driver data */
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np->driver_data = id->driver_data;
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/* handle different descriptor versions */
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if (id->driver_data & DEV_HAS_HIGH_DMA) {
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/* packet format 3: supports 40-bit addressing */
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@ -2986,7 +3027,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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}
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err = -ENOMEM;
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np->base = ioremap(addr, NV_PCI_REGSZ);
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np->base = ioremap(addr, np->register_size);
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if (!np->base)
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goto out_relreg;
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dev->base_addr = (unsigned long)np->base;
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@ -3062,6 +3103,20 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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writel(0, base + NvRegWakeUpFlags);
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np->wolenabled = 0;
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if (id->driver_data & DEV_HAS_POWER_CNTRL) {
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u8 revision_id;
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pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
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/* take phy and nic out of low power mode */
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powerstate = readl(base + NvRegPowerState2);
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powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
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if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
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id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
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revision_id >= 0xA3)
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powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
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writel(powerstate, base + NvRegPowerState2);
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}
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if (np->desc_ver == DESC_VER_1) {
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np->tx_flags = NV_TX_VALID;
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} else {
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@ -3223,19 +3278,19 @@ static struct pci_device_id pci_tbl[] = {
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},
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{ /* MCP51 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
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},
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{ /* MCP51 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
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},
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{ /* MCP55 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL,
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},
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{ /* MCP55 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL,
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},
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{0,},
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};
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