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ASoC: fsl-spdif: big-endian support

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For most platforms, the CPU and SPDIF device is in the same endianess
mode. While for the LS1 platform, the CPU is in LE mode and the SPDIF
is in BE mode.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Xiubo Li 2014-02-11 15:42:48 +08:00 committed by Mark Brown
parent 38dbfb59d1
commit 86f28d7643
2 changed files with 9 additions and 1 deletions
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5
Documentation/devicetree/bindings/sound/fsl,spdif.txt
View File

@ -29,6 +29,10 @@ Required properties:
can also be referred to TxClk_Source
bit of register SPDIF_STC.
- big-endian : If this property is absent, the native endian mode will
be in use as default, or the big endian mode will be in use for all the
device registers.
Example:
spdif: spdif@02004000 {
@ -50,5 +54,6 @@ spdif: spdif@02004000 {
"rxtx5", "rxtx6",
"rxtx7";
big-endian;
status = "okay";
};

5
sound/soc/fsl/fsl_spdif.c
View File

@ -985,7 +985,7 @@ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
}
}
static const struct regmap_config fsl_spdif_regmap_config = {
static struct regmap_config fsl_spdif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
@ -1105,6 +1105,9 @@ static int fsl_spdif_probe(struct platform_device *pdev)
memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
spdif_priv->cpu_dai_drv.name = spdif_priv->name;
if (of_property_read_bool(np, "big-endian"))
fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
/* Get the addresses and IRQ */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(&pdev->dev, res);