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[SCSI] megaraid_sas: Add new megaraid SAS 2 controller support to the driver
Add the new megaraid sas 2 controller to the driver. megaraid sas2 is LSI next generation SAS products. driver add the interface to support this product. Signed-off-by Bo Yang<bo.yang@lsi.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
Yang, Bo
James Bottomley
parent
72c4fd36dc
commit
879111224d
@ -76,6 +76,10 @@ static struct pci_device_id megasas_pci_table[] = {
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/* gen2*/
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0079GEN2)},
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/* gen2*/
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0073SKINNY)},
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/* skinny*/
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0071SKINNY)},
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/* skinny*/
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_VERDE_ZCR)},
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/* xscale IOP, vega */
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{PCI_DEVICE(PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_PERC5)},
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@ -334,6 +338,99 @@ static struct megasas_instance_template megasas_instance_template_ppc = {
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.read_fw_status_reg = megasas_read_fw_status_reg_ppc,
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};
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/**
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* megasas_enable_intr_skinny - Enables interrupts
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* @regs: MFI register set
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*/
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static inline void
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megasas_enable_intr_skinny(struct megasas_register_set __iomem *regs)
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{
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writel(0xFFFFFFFF, &(regs)->outbound_intr_mask);
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writel(~MFI_SKINNY_ENABLE_INTERRUPT_MASK, &(regs)->outbound_intr_mask);
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/* Dummy readl to force pci flush */
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readl(®s->outbound_intr_mask);
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}
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/**
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* megasas_disable_intr_skinny - Disables interrupt
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* @regs: MFI register set
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*/
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static inline void
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megasas_disable_intr_skinny(struct megasas_register_set __iomem *regs)
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{
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u32 mask = 0xFFFFFFFF;
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writel(mask, ®s->outbound_intr_mask);
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/* Dummy readl to force pci flush */
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readl(®s->outbound_intr_mask);
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}
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/**
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* megasas_read_fw_status_reg_skinny - returns the current FW status value
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* @regs: MFI register set
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*/
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static u32
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megasas_read_fw_status_reg_skinny(struct megasas_register_set __iomem *regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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}
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/**
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* megasas_clear_interrupt_skinny - Check & clear interrupt
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* @regs: MFI register set
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*/
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static int
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megasas_clear_intr_skinny(struct megasas_register_set __iomem *regs)
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{
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u32 status;
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/*
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* Check if it is our interrupt
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*/
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status = readl(®s->outbound_intr_status);
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if (!(status & MFI_SKINNY_ENABLE_INTERRUPT_MASK)) {
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return 1;
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}
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/*
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* Clear the interrupt by writing back the same value
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*/
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writel(status, ®s->outbound_intr_status);
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/*
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* dummy read to flush PCI
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*/
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readl(®s->outbound_intr_status);
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return 0;
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}
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/**
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* megasas_fire_cmd_skinny - Sends command to the FW
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* @frame_phys_addr : Physical address of cmd
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* @frame_count : Number of frames for the command
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* @regs : MFI register set
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*/
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static inline void
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megasas_fire_cmd_skinny(dma_addr_t frame_phys_addr, u32 frame_count,
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struct megasas_register_set __iomem *regs)
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{
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writel(0, &(regs)->inbound_high_queue_port);
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writel((frame_phys_addr | (frame_count<<1))|1,
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&(regs)->inbound_low_queue_port);
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}
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static struct megasas_instance_template megasas_instance_template_skinny = {
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.fire_cmd = megasas_fire_cmd_skinny,
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.enable_intr = megasas_enable_intr_skinny,
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.disable_intr = megasas_disable_intr_skinny,
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.clear_intr = megasas_clear_intr_skinny,
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.read_fw_status_reg = megasas_read_fw_status_reg_skinny,
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};
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/**
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* The following functions are defined for gen2 (deviceid : 0x78 0x79)
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* controllers
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@ -1587,16 +1684,34 @@ megasas_transition_to_ready(struct megasas_instance* instance)
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/*
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* Set the CLR bit in inbound doorbell
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*/
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writel(MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG,
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&instance->reg_set->inbound_doorbell);
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if ((instance->pdev->device == \
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PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
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(instance->pdev->device ==
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PCI_DEVICE_ID_LSI_SAS0071SKINNY)) {
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writel(
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MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG,
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&instance->reg_set->reserved_0[0]);
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} else {
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writel(
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MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG,
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&instance->reg_set->inbound_doorbell);
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}
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max_wait = 2;
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cur_state = MFI_STATE_WAIT_HANDSHAKE;
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break;
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case MFI_STATE_BOOT_MESSAGE_PENDING:
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writel(MFI_INIT_HOTPLUG,
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&instance->reg_set->inbound_doorbell);
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if ((instance->pdev->device ==
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PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
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(instance->pdev->device ==
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PCI_DEVICE_ID_LSI_SAS0071SKINNY)) {
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writel(MFI_INIT_HOTPLUG,
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&instance->reg_set->reserved_0[0]);
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} else
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writel(MFI_INIT_HOTPLUG,
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&instance->reg_set->inbound_doorbell);
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max_wait = 10;
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cur_state = MFI_STATE_BOOT_MESSAGE_PENDING;
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@ -1607,7 +1722,15 @@ megasas_transition_to_ready(struct megasas_instance* instance)
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* Bring it to READY state; assuming max wait 10 secs
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*/
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instance->instancet->disable_intr(instance->reg_set);
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writel(MFI_RESET_FLAGS, &instance->reg_set->inbound_doorbell);
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if ((instance->pdev->device ==
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PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
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(instance->pdev->device ==
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PCI_DEVICE_ID_LSI_SAS0071SKINNY)) {
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writel(MFI_RESET_FLAGS,
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&instance->reg_set->reserved_0[0]);
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} else
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writel(MFI_RESET_FLAGS,
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&instance->reg_set->inbound_doorbell);
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max_wait = 60;
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cur_state = MFI_STATE_OPERATIONAL;
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@ -2112,6 +2235,8 @@ static int megasas_init_mfi(struct megasas_instance *instance)
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* Map the message registers
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*/
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if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS1078GEN2) ||
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(instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0071SKINNY) ||
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(instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0073SKINNY) ||
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(instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0079GEN2)) {
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instance->base_addr = pci_resource_start(instance->pdev, 1);
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} else {
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@ -2142,6 +2267,10 @@ static int megasas_init_mfi(struct megasas_instance *instance)
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case PCI_DEVICE_ID_LSI_SAS0079GEN2:
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instance->instancet = &megasas_instance_template_gen2;
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break;
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case PCI_DEVICE_ID_LSI_SAS0073SKINNY:
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case PCI_DEVICE_ID_LSI_SAS0071SKINNY:
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instance->instancet = &megasas_instance_template_skinny;
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break;
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case PCI_DEVICE_ID_LSI_SAS1064R:
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case PCI_DEVICE_ID_DELL_PERC5:
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default:
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@ -30,6 +30,8 @@
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#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
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#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
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#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
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#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
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#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
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/*
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* =====================================
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@ -584,6 +586,8 @@ struct megasas_ctrl_info {
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#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
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#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
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#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
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#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
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#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
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/*
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* register set for both 1068 and 1078 controllers
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