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x86, AMD, NB: Use u16 for northbridge IDs in amd_get_nb_id

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Change amd_get_nb_id to return u16 to support >255 memory controllers,
and related consistency fixes.

Signed-off-by: Daniel J Blueman <daniel@numascale-asia.com>
Link: http://lkml.kernel.org/r/1353997932-8475-2-git-send-email-daniel@numascale-asia.com
Signed-off-by: Borislav Petkov <bp@alien8.de>
This commit is contained in:
Daniel J Blueman 2012-11-27 14:32:10 +08:00 committed by Borislav Petkov
parent 772c3ff385
commit 8b84c8df38
3 changed files with 6 additions and 5 deletions
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2
arch/x86/include/asm/processor.h
View File

@ -943,7 +943,7 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
extern int get_tsc_mode(unsigned long adr);
extern int set_tsc_mode(unsigned int val);
extern int amd_get_nb_id(int cpu);
extern u16 amd_get_nb_id(int cpu);
struct aperfmperf {
u64 aperf, mperf;

4
arch/x86/kernel/cpu/amd.c
View File

@ -364,9 +364,9 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
#endif
}
int amd_get_nb_id(int cpu)
u16 amd_get_nb_id(int cpu)
{
int id = 0;
u16 id = 0;
#ifdef CONFIG_SMP
id = per_cpu(cpu_llc_id, cpu);
#endif

5
drivers/edac/amd64_edac.c
View File

@ -939,7 +939,8 @@ static u64 get_error_address(struct mce *m)
struct amd64_pvt *pvt;
u64 cc6_base, tmp_addr;
u32 tmp;
u8 mce_nid, intlv_en;
u16 mce_nid;
u8 intlv_en;
if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
return addr;
@ -2181,7 +2182,7 @@ static int init_csrows(struct mem_ctl_info *mci)
}
/* get all cores on this DCT */
static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid)
static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
{
int cpu;