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ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant

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A typical SMP system expects cache coherency. Initial NPS platform
support was slated to be SMP w/o cache coherency.

However it seems the platform now selects that option, so there is no
point in keeping it around.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2017-02-02 09:09:50 -08:00
parent b48fba057c
commit 8ba605b607
3 changed files with 0 additions and 8 deletions
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6
arch/arc/Kconfig
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@ -180,16 +180,12 @@ config CPU_BIG_ENDIAN
config SMP
bool "Symmetric Multi-Processing"
default n
select ARC_HAS_COH_CACHES if ISA_ARCV2
select ARC_MCIP if ISA_ARCV2
help
This enables support for systems with more than one CPU.
if SMP
config ARC_HAS_COH_CACHES
def_bool n
config NR_CPUS
int "Maximum number of CPUs (2-4096)"
range 2 4096
@ -219,8 +215,6 @@ config ARC_MCIP
menuconfig ARC_CACHE
bool "Enable Cache Support"
default y
# if SMP, cache enabled ONLY if ARC implementation has cache coherency
depends on !SMP || ARC_HAS_COH_CACHES
if ARC_CACHE

1
arch/arc/plat-eznps/Kconfig
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@ -5,7 +5,6 @@
menuconfig ARC_PLAT_EZNPS
bool "\"EZchip\" ARC dev platform"
select ARC_HAS_COH_CACHES if SMP
select CPU_BIG_ENDIAN
select CLKSRC_NPS
select EZNPS_GIC

1
arch/arc/plat-sim/Kconfig
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@ -8,7 +8,6 @@
menuconfig ARC_PLAT_SIM
bool "ARC nSIM based simulation virtual platforms"
select ARC_HAS_COH_CACHES if SMP
help
Support for nSIM based ARC simulation platforms
This includes the standalone nSIM (uart only) vs. System C OSCI VP