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sh: sh7786 mstp32 index rework
This patch adds sh7786 MSTP enums for mstp_clks[] index. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
eb85dcaa3e
commit
8bc23d95a0
@ -87,39 +87,47 @@ struct clk div4_clks[DIV4_NR] = {
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#define MSTPCR0 0xffc40030
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#define MSTPCR1 0xffc40034
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static struct clk mstp_clks[] = {
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enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
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MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
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MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
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MSTP005, MSTP004, MSTP002,
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MSTP112, MSTP110, MSTP109, MSTP108,
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MSTP105, MSTP104, MSTP103, MSTP102,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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/* MSTPCR0 */
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SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
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SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
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SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
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SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
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SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
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SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
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SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
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SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
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SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
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SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
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SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
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SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
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SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
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SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
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SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
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SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
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SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
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SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
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SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
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SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
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SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
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[MSTP029] = SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
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[MSTP028] = SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
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[MSTP027] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
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[MSTP026] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
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[MSTP025] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
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[MSTP024] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
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[MSTP023] = SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
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[MSTP022] = SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
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[MSTP021] = SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
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[MSTP020] = SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
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[MSTP017] = SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
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[MSTP016] = SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
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[MSTP015] = SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
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[MSTP014] = SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
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[MSTP011] = SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
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[MSTP010] = SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
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[MSTP009] = SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
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[MSTP008] = SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
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[MSTP005] = SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
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[MSTP004] = SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
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[MSTP002] = SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
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/* MSTPCR1 */
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SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
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SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
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SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
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SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
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SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
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SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
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SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
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SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
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[MSTP112] = SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
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[MSTP110] = SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
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[MSTP109] = SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
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[MSTP108] = SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
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[MSTP105] = SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
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[MSTP104] = SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
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[MSTP103] = SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
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[MSTP102] = SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
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};
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static struct clk_lookup lookups[] = {
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@ -127,62 +135,62 @@ static struct clk_lookup lookups[] = {
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/* TMU0 */
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.dev_id = "sh_tmu.0",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[17], /* tmu012_fck */
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.clk = &mstp_clks[MSTP008],
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}, {
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/* TMU1 */
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.dev_id = "sh_tmu.1",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[17],
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.clk = &mstp_clks[MSTP008],
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}, {
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/* TMU2 */
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.dev_id = "sh_tmu.2",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[17],
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.clk = &mstp_clks[MSTP008],
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}, {
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/* TMU3 */
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.dev_id = "sh_tmu.3",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[16], /* tmu345_fck */
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.clk = &mstp_clks[MSTP009],
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}, {
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/* TMU4 */
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.dev_id = "sh_tmu.4",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[16],
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.clk = &mstp_clks[MSTP009],
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}, {
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/* TMU5 */
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.dev_id = "sh_tmu.5",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[16],
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.clk = &mstp_clks[MSTP009],
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}, {
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/* TMU6 */
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.dev_id = "sh_tmu.6",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[15], /* tmu678_fck */
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.clk = &mstp_clks[MSTP010],
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}, {
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/* TMU7 */
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.dev_id = "sh_tmu.7",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[15],
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.clk = &mstp_clks[MSTP010],
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}, {
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/* TMU8 */
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.dev_id = "sh_tmu.8",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[15],
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.clk = &mstp_clks[MSTP010],
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}, {
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/* TMU9 */
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.dev_id = "sh_tmu.9",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[14], /* tmu9_11_fck */
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.clk = &mstp_clks[MSTP011],
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}, {
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/* TMU10 */
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.dev_id = "sh_tmu.10",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[14],
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.clk = &mstp_clks[MSTP011],
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}, {
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/* TMU11 */
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.dev_id = "sh_tmu.11",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[14],
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.clk = &mstp_clks[MSTP011],
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}
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};
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@ -199,7 +207,7 @@ int __init arch_clk_init(void)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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return ret;
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}
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