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ath9k: Add open loop control support
This patch adds Open Loop Control support for Atheros chipsets that supports open loop power control. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Senthil Balasubramanian
John W. Linville
parent
81cb7623ad
commit
8bd1d07f93
@ -718,10 +718,39 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
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return nf;
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}
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static void ath9k_olc_temp_compensation(struct ath_hw *ah)
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{
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u32 rddata, i;
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int delta, currPDADC, regval;
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rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
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currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
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if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
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delta = (currPDADC - ah->initPDADC + 4) / 8;
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else
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delta = (currPDADC - ah->initPDADC + 5) / 10;
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if (delta != ah->PDADCdelta) {
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ah->PDADCdelta = delta;
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for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
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regval = ah->originalGain[i] - delta;
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if (regval < 0)
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regval = 0;
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REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4,
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AR_PHY_TX_GAIN, regval);
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}
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}
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}
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bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
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u8 rxchainmask, bool longcal,
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bool *isCalDone)
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{
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#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
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ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
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struct hal_cal_list *currCal = ah->cal_list_curr;
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*isCalDone = true;
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@ -742,6 +771,8 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
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}
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if (longcal) {
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if (OLC_FOR_AR9280_20_LATER)
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ath9k_olc_temp_compensation(ah);
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ath9k_hw_getnf(ah, chan);
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ath9k_hw_loadnf(ah, ah->curchan);
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ath9k_hw_start_nfcal(ah);
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@ -179,6 +179,69 @@ static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
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}
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}
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static void ath9k_get_txgain_index(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct calDataPerFreqOpLoop *rawDatasetOpLoop,
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u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
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{
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u8 pcdac, i = 0;
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u16 idxL = 0, idxR = 0, numPiers;
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bool match;
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struct chan_centers centers;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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for (numPiers = 0; numPiers < availPiers; numPiers++)
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if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
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break;
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match = ath9k_hw_get_lower_upper_index(
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(u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
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calChans, numPiers, &idxL, &idxR);
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if (match) {
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pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
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*pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
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} else {
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pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
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*pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
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rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
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}
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while (pcdac > ah->originalGain[i] &&
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i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
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i++;
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*pcdacIdx = i;
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return;
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}
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static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
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u32 initTxGain,
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int txPower,
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u8 *pPDADCValues)
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{
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u32 i;
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u32 offset;
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REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
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AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
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REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
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AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
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REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
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AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
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offset = txPower;
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for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
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if (i < offset)
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pPDADCValues[i] = 0x0;
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else
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pPDADCValues[i] = 0xFF;
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}
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static void ath9k_hw_get_target_powers(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct cal_target_power_ht *powInfo,
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@ -1596,6 +1659,16 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
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return pBase->rxGainType;
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case EEP_TXGAIN_TYPE:
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return pBase->txGainType;
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case EEP_OL_PWRCTRL:
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if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
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return pBase->openLoopPwrCntl ? true : false;
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else
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return false;
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case EEP_RC_CHAIN_MASK:
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if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
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return pBase->rcChainMask;
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else
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return 0;
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case EEP_DAC_HPWR_5G:
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if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
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return pBase->dacHiPwrMode_5G;
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@ -1839,8 +1912,15 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
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pModal->swSettleHt40);
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}
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if (AR_SREV_9280_20_OR_LATER(ah) &&
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AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
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REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
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AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
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pModal->miscBits);
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if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
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if (IS_CHAN_HT20(chan))
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if (IS_CHAN_2GHZ(chan))
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REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
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eep->baseEepHeader.dacLpMode);
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else if (eep->baseEepHeader.dacHiPwrMode_5G)
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@ -1851,6 +1931,10 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
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REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
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pModal->miscBits >> 2);
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REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
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AR_PHY_TX_DESIRED_SCALE_CCK,
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eep->baseEepHeader.desiredScaleCCK);
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}
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return true;
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@ -2080,6 +2164,12 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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struct ath9k_channel *chan,
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int16_t *pTxPowerIndexOffset)
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{
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#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
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ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
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#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
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#define SM_PDGAIN_B(x, y) \
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SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
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struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
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struct cal_data_per_freq *pRawDataset;
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u8 *pCalBChans = NULL;
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@ -2113,6 +2203,12 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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numPiers = AR5416_NUM_5G_CAL_PIERS;
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}
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if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
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pRawDataset = pEepData->calPierData2G[0];
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ah->initPDADC = ((struct calDataPerFreqOpLoop *)
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pRawDataset)->vpdPdg[0][0];
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}
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numXpdGain = 0;
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for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
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@ -2148,25 +2244,45 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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else
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pRawDataset = pEepData->calPierData5G[i];
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ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan,
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pRawDataset, pCalBChans,
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numPiers, pdGainOverlap_t2,
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&tMinCalPower, gainBoundaries,
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pdadcValues, numXpdGain);
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if (OLC_FOR_AR9280_20_LATER) {
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u8 pcdacIdx;
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u8 txPower;
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ath9k_get_txgain_index(ah, chan,
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(struct calDataPerFreqOpLoop *)pRawDataset,
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pCalBChans, numPiers, &txPower, &pcdacIdx);
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ath9k_olc_get_pdadcs(ah, pcdacIdx,
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txPower/2, pdadcValues);
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} else {
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ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
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chan, pRawDataset,
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pCalBChans, numPiers,
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pdGainOverlap_t2,
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&tMinCalPower,
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gainBoundaries,
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pdadcValues,
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numXpdGain);
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}
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if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
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REG_WRITE(ah,
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AR_PHY_TPCRG5 + regChainOffset,
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SM(pdGainOverlap_t2,
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
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| SM(gainBoundaries[0],
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AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
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| SM(gainBoundaries[1],
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AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
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| SM(gainBoundaries[2],
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AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
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| SM(gainBoundaries[3],
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AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
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if (OLC_FOR_AR9280_20_LATER) {
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REG_WRITE(ah,
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AR_PHY_TPCRG5 + regChainOffset,
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SM(0x6,
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
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SM_PD_GAIN(1) | SM_PD_GAIN(2) |
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SM_PD_GAIN(3) | SM_PD_GAIN(4));
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} else {
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REG_WRITE(ah,
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AR_PHY_TPCRG5 + regChainOffset,
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SM(pdGainOverlap_t2,
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
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SM_PDGAIN_B(0, 1) |
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SM_PDGAIN_B(1, 2) |
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SM_PDGAIN_B(2, 3) |
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SM_PDGAIN_B(3, 4));
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}
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}
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regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
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@ -2200,6 +2316,8 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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*pTxPowerIndexOffset = 0;
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return true;
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#undef SM_PD_GAIN
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#undef SM_PDGAIN_B
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}
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static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
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@ -2500,13 +2618,14 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
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u8 twiceMaxRegulatoryPower,
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u8 powerLimit)
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{
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#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
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struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
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struct modal_eep_header *pModal =
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&(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
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int16_t ratesArray[Ar5416RateSize];
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int16_t txPowerIndexOffset = 0;
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u8 ht40PowerIncForPdadc = 2;
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int i;
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int i, cck_ofdm_delta = 0;
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memset(ratesArray, 0, sizeof(ratesArray));
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@ -2555,16 +2674,30 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
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| ATH9K_POW_SM(ratesArray[rate24mb], 0));
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if (IS_CHAN_2GHZ(chan)) {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
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ATH9K_POW_SM(ratesArray[rate2s], 24)
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| ATH9K_POW_SM(ratesArray[rate2l], 16)
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| ATH9K_POW_SM(ratesArray[rateXr], 8)
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| ATH9K_POW_SM(ratesArray[rate1l], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
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ATH9K_POW_SM(ratesArray[rate11s], 24)
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| ATH9K_POW_SM(ratesArray[rate11l], 16)
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| ATH9K_POW_SM(ratesArray[rate5_5s], 8)
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| ATH9K_POW_SM(ratesArray[rate5_5l], 0));
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if (OLC_FOR_AR9280_20_LATER) {
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cck_ofdm_delta = 2;
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
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ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
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| ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
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| ATH9K_POW_SM(ratesArray[rateXr], 8)
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| ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
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ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
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| ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
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| ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
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| ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
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} else {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
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ATH9K_POW_SM(ratesArray[rate2s], 24)
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| ATH9K_POW_SM(ratesArray[rate2l], 16)
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| ATH9K_POW_SM(ratesArray[rateXr], 8)
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| ATH9K_POW_SM(ratesArray[rate1l], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
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ATH9K_POW_SM(ratesArray[rate11s], 24)
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| ATH9K_POW_SM(ratesArray[rate11l], 16)
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| ATH9K_POW_SM(ratesArray[rate5_5s], 8)
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| ATH9K_POW_SM(ratesArray[rate5_5l], 0));
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}
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}
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
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@ -2597,12 +2730,19 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
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ht40PowerIncForPdadc, 8)
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| ATH9K_POW_SM(ratesArray[rateHt40_4] +
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ht40PowerIncForPdadc, 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
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ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
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| ATH9K_POW_SM(ratesArray[rateExtCck], 16)
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| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
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| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
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if (OLC_FOR_AR9280_20_LATER) {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
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ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
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| ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
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| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
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| ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
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} else {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
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ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
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| ATH9K_POW_SM(ratesArray[rateExtCck], 16)
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| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
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| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
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}
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}
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REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
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@ -168,6 +168,8 @@
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#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
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#define AR5416_EEP4K_MAX_CHAINS 1
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#define AR9280_TX_GAIN_TABLE_SIZE 22
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enum eeprom_param {
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EEP_NFTHRESH_5,
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EEP_NFTHRESH_2,
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@ -188,6 +190,8 @@ enum eeprom_param {
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EEP_RX_MASK,
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EEP_RXGAIN_TYPE,
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EEP_TXGAIN_TYPE,
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EEP_OL_PWRCTRL,
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EEP_RC_CHAIN_MASK,
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EEP_DAC_HPWR_5G,
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EEP_FRAC_N_5G
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};
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@ -229,7 +233,7 @@ struct base_eep_header {
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u8 futureBase_1[2];
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u8 rxGainType;
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u8 dacHiPwrMode_5G;
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u8 futureBase_2;
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u8 openLoopPwrCntl;
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u8 dacLpMode;
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u8 txGainType;
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u8 rcChainMask;
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@ -310,6 +314,13 @@ struct modal_eep_header {
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struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
|
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} __packed;
|
||||
|
||||
struct calDataPerFreqOpLoop {
|
||||
u8 pwrPdg[2][5];
|
||||
u8 vpdPdg[2][5];
|
||||
u8 pcdac[2][5];
|
||||
u8 empty[2][5];
|
||||
} __packed;
|
||||
|
||||
struct modal_eep_4k_header {
|
||||
u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
|
||||
u32 antCtrlCommon;
|
||||
|
||||
@ -1202,10 +1202,23 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
|
||||
return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
|
||||
}
|
||||
|
||||
static void ath9k_olc_init(struct ath_hw *ah)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
|
||||
ah->originalGain[i] =
|
||||
MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
|
||||
AR_PHY_TX_GAIN);
|
||||
ah->PDADCdelta = 0;
|
||||
}
|
||||
|
||||
static int ath9k_hw_process_ini(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan,
|
||||
enum ath9k_ht_macmode macmode)
|
||||
{
|
||||
#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
|
||||
ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
|
||||
int i, regWrites = 0;
|
||||
struct ieee80211_channel *channel = chan->chan;
|
||||
u32 modesIndex, freqIndex;
|
||||
@ -1308,6 +1321,9 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
|
||||
ath9k_hw_set_regs(ah, chan, macmode);
|
||||
ath9k_hw_init_chain_masks(ah);
|
||||
|
||||
if (OLC_FOR_AR9280_20_LATER)
|
||||
ath9k_olc_init(ah);
|
||||
|
||||
status = ah->eep_ops->set_txpower(ah, chan,
|
||||
ath9k_regd_get_ctl(ah, chan),
|
||||
channel->max_antenna_gain * 2,
|
||||
@ -1515,6 +1531,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
|
||||
AR_RTC_FORCE_WAKE_ON_INT);
|
||||
|
||||
REG_WRITE(ah, AR_RTC_RESET, 0);
|
||||
udelay(2);
|
||||
REG_WRITE(ah, AR_RTC_RESET, 1);
|
||||
|
||||
if (!ath9k_hw_wait(ah,
|
||||
@ -1582,7 +1599,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
|
||||
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan)
|
||||
{
|
||||
if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
|
||||
if (OLC_FOR_AR9280_20_LATER) {
|
||||
if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
|
||||
return false;
|
||||
} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
|
||||
return false;
|
||||
|
||||
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
|
||||
@ -3404,6 +3424,10 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
|
||||
return 0;
|
||||
}
|
||||
return false;
|
||||
case ATH9K_CAP_DS:
|
||||
return (AR_SREV_9280_20_OR_LATER(ah) &&
|
||||
(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
|
||||
? false : true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -162,7 +162,8 @@ enum ath9k_capability_type {
|
||||
ATH9K_CAP_WME_TKIPMIC,
|
||||
ATH9K_CAP_RFSILENT,
|
||||
ATH9K_CAP_ANT_CFG_2GHZ,
|
||||
ATH9K_CAP_ANT_CFG_5GHZ
|
||||
ATH9K_CAP_ANT_CFG_5GHZ,
|
||||
ATH9K_CAP_DS
|
||||
};
|
||||
|
||||
struct ath9k_hw_capabilities {
|
||||
@ -551,6 +552,10 @@ struct ath_hw {
|
||||
u8 txchainmask;
|
||||
u8 rxchainmask;
|
||||
|
||||
u32 originalGain[22];
|
||||
int initPDADC;
|
||||
int PDADCdelta;
|
||||
|
||||
struct ar5416IniArray iniModes;
|
||||
struct ar5416IniArray iniCommon;
|
||||
struct ar5416IniArray iniBank0;
|
||||
|
||||
@ -387,6 +387,8 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
|
||||
|
||||
#define AR_PHY_CCK_TX_CTRL 0xA204
|
||||
#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
|
||||
#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
|
||||
#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
|
||||
|
||||
#define AR_PHY_CCK_DETECT 0xA208
|
||||
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
|
||||
@ -444,6 +446,29 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
|
||||
|
||||
#define AR_PHY_TX_PWRCTRL4 0xa264
|
||||
#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
|
||||
#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
|
||||
#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
|
||||
#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
|
||||
|
||||
#define AR_PHY_TX_PWRCTRL6_0 0xa270
|
||||
#define AR_PHY_TX_PWRCTRL6_1 0xb270
|
||||
#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
|
||||
#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
|
||||
|
||||
#define AR_PHY_TX_PWRCTRL7 0xa274
|
||||
#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
|
||||
#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
|
||||
|
||||
#define AR_PHY_TX_PWRCTRL9 0xa27C
|
||||
#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
|
||||
#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
|
||||
|
||||
#define AR_PHY_TX_GAIN_TBL1 0xa300
|
||||
#define AR_PHY_TX_GAIN 0x0007F000
|
||||
#define AR_PHY_TX_GAIN_S 12
|
||||
|
||||
#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
|
||||
#define AR_PHY_MASK2_M_31_45 0xa3a4
|
||||
#define AR_PHY_MASK2_M_16_30 0xa3a8
|
||||
|
||||
@ -1392,6 +1392,7 @@ static void ath_rc_init(struct ath_softc *sc,
|
||||
struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
|
||||
u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates;
|
||||
u8 i, j, k, hi = 0, hthi = 0;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
|
||||
/* FIXME: Adhoc */
|
||||
if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) ||
|
||||
@ -1412,7 +1413,8 @@ static void ath_rc_init(struct ath_softc *sc,
|
||||
|
||||
if (sta->ht_cap.ht_supported) {
|
||||
ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG;
|
||||
if (sc->sc_ah->caps.tx_chainmask != 1)
|
||||
if (sc->sc_ah->caps.tx_chainmask != 1 &&
|
||||
ath9k_hw_getcapability(ah, ATH9K_CAP_DS, 0, NULL))
|
||||
ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG;
|
||||
if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
|
||||
ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user