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drm/i915: split page flip queueing into per-chipset functions
This makes things a little clearer and prevents us from running old code on a new chipset that may not be supported. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewied-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Jesse Barnes
Keith Packard
parent
483f179899
commit
8c9f3aaf8e
@ -211,6 +211,9 @@ struct drm_i915_display_funcs {
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*init_clock_gating)(struct drm_device *dev);
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void (*init_pch_clock_gating)(struct drm_device *dev);
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int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj);
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/* clock updates for mode set */
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/* cursor updates */
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/* render clock increase/decrease */
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@ -6261,6 +6261,164 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static int intel_gen2_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long offset;
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u32 flip_mask;
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int ret;
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ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
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if (ret)
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goto out;
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/* Offset into the new buffer for cases of shared fbs between CRTCs */
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offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
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ret = BEGIN_LP_RING(6);
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if (ret)
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goto out;
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/* Can't queue multiple flips, so wait for the previous
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* one to finish before executing the next.
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*/
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
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OUT_RING(MI_NOOP);
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(obj->gtt_offset + offset);
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OUT_RING(MI_NOOP);
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ADVANCE_LP_RING();
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out:
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return ret;
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}
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static int intel_gen3_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long offset;
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u32 flip_mask;
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int ret;
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ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
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if (ret)
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goto out;
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/* Offset into the new buffer for cases of shared fbs between CRTCs */
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offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
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ret = BEGIN_LP_RING(6);
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if (ret)
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goto out;
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
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OUT_RING(MI_NOOP);
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OUT_RING(MI_DISPLAY_FLIP_I915 |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(obj->gtt_offset + offset);
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OUT_RING(MI_NOOP);
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ADVANCE_LP_RING();
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out:
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return ret;
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}
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static int intel_gen4_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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uint32_t pf, pipesrc;
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int ret;
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ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
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if (ret)
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goto out;
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ret = BEGIN_LP_RING(4);
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if (ret)
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goto out;
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/* i965+ uses the linear or tiled offsets from the
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* Display Registers (which do not change across a page-flip)
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* so we need only reprogram the base address.
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*/
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(obj->gtt_offset | obj->tiling_mode);
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/* XXX Enabling the panel-fitter across page-flip is so far
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* untested on non-native modes, so ignore it for now.
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* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
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*/
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pf = 0;
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pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
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OUT_RING(pf | pipesrc);
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ADVANCE_LP_RING();
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out:
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return ret;
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}
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static int intel_gen6_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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uint32_t pf, pipesrc;
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int ret;
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ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
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if (ret)
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goto out;
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ret = BEGIN_LP_RING(4);
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if (ret)
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goto out;
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch | obj->tiling_mode);
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OUT_RING(obj->gtt_offset);
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pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
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pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
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OUT_RING(pf | pipesrc);
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ADVANCE_LP_RING();
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out:
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return ret;
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}
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static int intel_default_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj)
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{
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return -ENODEV;
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}
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static int intel_crtc_page_flip(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event)
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@ -6271,9 +6429,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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struct drm_i915_gem_object *obj;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_unpin_work *work;
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unsigned long flags, offset;
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int pipe = intel_crtc->pipe;
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u32 pf, pipesrc;
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unsigned long flags;
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int ret;
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work = kzalloc(sizeof *work, GFP_KERNEL);
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@ -6302,9 +6458,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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obj = intel_fb->obj;
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mutex_lock(&dev->struct_mutex);
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ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
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if (ret)
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goto cleanup_work;
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/* Reference the objects for the scheduled work. */
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drm_gem_object_reference(&work->old_fb_obj->base);
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@ -6316,91 +6469,18 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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if (ret)
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goto cleanup_objs;
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if (IS_GEN3(dev) || IS_GEN2(dev)) {
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u32 flip_mask;
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/* Can't queue multiple flips, so wait for the previous
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* one to finish before executing the next.
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*/
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ret = BEGIN_LP_RING(2);
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if (ret)
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goto cleanup_objs;
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
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OUT_RING(MI_NOOP);
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ADVANCE_LP_RING();
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}
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work->pending_flip_obj = obj;
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work->enable_stall_check = true;
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/* Offset into the new buffer for cases of shared fbs between CRTCs */
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offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
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ret = BEGIN_LP_RING(4);
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if (ret)
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goto cleanup_objs;
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/* Block clients from rendering to the new back buffer until
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* the flip occurs and the object is no longer visible.
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*/
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atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
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switch (INTEL_INFO(dev)->gen) {
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case 2:
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(obj->gtt_offset + offset);
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OUT_RING(MI_NOOP);
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break;
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case 3:
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OUT_RING(MI_DISPLAY_FLIP_I915 |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(obj->gtt_offset + offset);
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OUT_RING(MI_NOOP);
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break;
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case 4:
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case 5:
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/* i965+ uses the linear or tiled offsets from the
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* Display Registers (which do not change across a page-flip)
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* so we need only reprogram the base address.
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*/
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(obj->gtt_offset | obj->tiling_mode);
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/* XXX Enabling the panel-fitter across page-flip is so far
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* untested on non-native modes, so ignore it for now.
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* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
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*/
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pf = 0;
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pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
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OUT_RING(pf | pipesrc);
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break;
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case 6:
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case 7:
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch | obj->tiling_mode);
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OUT_RING(obj->gtt_offset);
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pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
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pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
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OUT_RING(pf | pipesrc);
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break;
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}
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ADVANCE_LP_RING();
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ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
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if (ret)
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goto cleanup_pending;
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mutex_unlock(&dev->struct_mutex);
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@ -6408,10 +6488,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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return 0;
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cleanup_pending:
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atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
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cleanup_objs:
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drm_gem_object_unreference(&work->old_fb_obj->base);
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drm_gem_object_unreference(&obj->base);
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cleanup_work:
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mutex_unlock(&dev->struct_mutex);
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spin_lock_irqsave(&dev->event_lock, flags);
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@ -7656,6 +7737,28 @@ static void intel_init_display(struct drm_device *dev)
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else
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dev_priv->display.get_fifo_size = i830_get_fifo_size;
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}
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/* Default just returns -ENODEV to indicate unsupported */
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dev_priv->display.queue_flip = intel_default_queue_flip;
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switch (INTEL_INFO(dev)->gen) {
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case 2:
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dev_priv->display.queue_flip = intel_gen2_queue_flip;
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break;
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case 3:
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dev_priv->display.queue_flip = intel_gen3_queue_flip;
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break;
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case 4:
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case 5:
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dev_priv->display.queue_flip = intel_gen4_queue_flip;
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break;
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case 6:
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dev_priv->display.queue_flip = intel_gen6_queue_flip;
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break;
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}
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}
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/*
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