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iwlwifi: refactor rx register initialization
The patch adds HW bug W/A FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY so that we can enable again interrupt coalescing. It also uses named constants for open code. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -64,7 +64,7 @@
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#define CSR_BASE (0x000)
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#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
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#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
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#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
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#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
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#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
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#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
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@ -247,8 +247,8 @@
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#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
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#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
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#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
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#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
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#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
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#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
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#define RX_RB_TIMEOUT (0x10)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
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@ -260,8 +260,9 @@
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
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#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
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/**
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@ -376,7 +376,9 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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{
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int ret;
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unsigned long flags;
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unsigned int rb_size;
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u32 rb_size;
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
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spin_lock_irqsave(&priv->lock, flags);
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ret = iwl_grab_nic_access(priv);
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@ -398,26 +400,32 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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/* Tell device where to find RBD circular buffer in DRAM */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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rxq->dma_addr >> 8);
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(u32)(rxq->dma_addr >> 8));
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/* Tell device where in DRAM to update its Rx status */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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(priv->shared_phys + priv->rb_closed_offset) >> 4);
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/* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
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/* Enable Rx DMA
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* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set becuase of HW bug in
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* the credit mechanism in 5000 HW RX FIFO
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* Direct rx interrupts to hosts
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* Rx buffer size 4 or 8k
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* RB timeout 0x10
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* 256 RBDs
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*/
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iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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rb_size |
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/* 0x10 << 4 | */
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(RX_QUEUE_SIZE_LOG <<
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FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
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/*
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* iwl_write32(priv,CSR_INT_COAL_REG,0);
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*/
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rb_size|
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(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
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(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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iwl_release_nic_access(priv);
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iwl_write32(priv, CSR_INT_COALESCING, 0x40);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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