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brcm80211: smac: use bcma core access functions in pmu.c
The code in pmu.c now uses the functions provided by BCMA to access the core registers. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Arend van Spriel
John W. Linville
parent
b14f16747f
commit
8d30b708b8
@ -140,7 +140,7 @@ static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
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}
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static void
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si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
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si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct bcma_device *core,
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u8 spuravoid)
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{
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u32 tmp = 0;
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@ -149,58 +149,65 @@ si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
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case BCM43224_CHIP_ID:
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case BCM43225_CHIP_ID:
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if (spuravoid == 1) {
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
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W_REG(&cc->pllcontrol_data, 0x11500010);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
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W_REG(&cc->pllcontrol_data, 0x000C0C06);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
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W_REG(&cc->pllcontrol_data, 0x0F600a08);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
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W_REG(&cc->pllcontrol_data, 0x00000000);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
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W_REG(&cc->pllcontrol_data, 0x2001E920);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
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W_REG(&cc->pllcontrol_data, 0x88888815);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL0);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x11500010);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL1);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x000C0C06);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL2);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x0F600a08);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL3);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x00000000);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL4);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x2001E920);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL5);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x88888815);
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} else {
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
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W_REG(&cc->pllcontrol_data, 0x11100010);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
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W_REG(&cc->pllcontrol_data, 0x000c0c06);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
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W_REG(&cc->pllcontrol_data, 0x03000a08);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
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W_REG(&cc->pllcontrol_data, 0x00000000);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
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W_REG(&cc->pllcontrol_data, 0x200005c0);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
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W_REG(&cc->pllcontrol_data, 0x88888815);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL0);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x11100010);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL1);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x000c0c06);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL2);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x03000a08);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL3);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x00000000);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL4);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x200005c0);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
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PMU1_PLL0_PLLCTL5);
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bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
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0x88888815);
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}
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tmp = 1 << 10;
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break;
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
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W_REG(&cc->pllcontrol_data, 0x11100008);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
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W_REG(&cc->pllcontrol_data, 0x0c000c06);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
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W_REG(&cc->pllcontrol_data, 0x03000a08);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
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W_REG(&cc->pllcontrol_data, 0x00000000);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
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W_REG(&cc->pllcontrol_data, 0x200005c0);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
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W_REG(&cc->pllcontrol_data, 0x88888855);
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tmp = 1 << 10;
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break;
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default:
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/* bail out */
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return;
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}
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tmp |= R_REG(&cc->pmucontrol);
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W_REG(&cc->pmucontrol, tmp);
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bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
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}
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u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
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@ -289,12 +296,12 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
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void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
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{
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struct chipcregs __iomem *cc;
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struct bcma_device *cc;
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uint origidx, intr_val;
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/* Remember original core before switch to chipc */
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cc = (struct chipcregs __iomem *)
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ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
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/* switch to chipc */
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cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
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/* update the pll changes */
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si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
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@ -306,20 +313,16 @@ void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
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/* initialize PMU */
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void si_pmu_init(struct si_pub *sih)
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{
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struct chipcregs __iomem *cc;
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uint origidx;
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struct bcma_device *core;
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/* Remember original core before switch to chipc */
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origidx = ai_coreidx(sih);
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cc = ai_setcoreidx(sih, SI_CC_IDX);
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/* select chipc */
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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if (ai_get_pmurev(sih) == 1)
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AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
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bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
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~PCTL_NOILP_ON_WAIT);
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else if (ai_get_pmurev(sih) >= 2)
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OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
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/* Return to original core */
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ai_setcoreidx(sih, origidx);
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bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
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}
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/* initialize PMU chip controls and other chip level stuff */
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@ -369,13 +372,11 @@ void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
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/* initialize PMU resources */
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void si_pmu_res_init(struct si_pub *sih)
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{
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struct chipcregs __iomem *cc;
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uint origidx;
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struct bcma_device *core;
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u32 min_mask = 0, max_mask = 0;
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/* Remember original core before switch to chipc */
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origidx = ai_coreidx(sih);
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cc = ai_setcoreidx(sih, SI_CC_IDX);
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/* select to chipc */
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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/* Determine min/max rsrc masks */
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si_pmu_res_masks(sih, &min_mask, &max_mask);
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@ -385,55 +386,50 @@ void si_pmu_res_init(struct si_pub *sih)
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/* Program max resource mask */
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if (max_mask)
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W_REG(&cc->max_res_mask, max_mask);
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bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
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/* Program min resource mask */
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if (min_mask)
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W_REG(&cc->min_res_mask, min_mask);
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bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
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/* Add some delay; allow resources to come up and settle. */
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mdelay(2);
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/* Return to original core */
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ai_setcoreidx(sih, origidx);
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}
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u32 si_pmu_measure_alpclk(struct si_pub *sih)
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{
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struct chipcregs __iomem *cc;
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uint origidx;
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struct bcma_device *core;
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u32 alp_khz;
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if (ai_get_pmurev(sih) < 10)
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return 0;
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/* Remember original core before switch to chipc */
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origidx = ai_coreidx(sih);
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cc = ai_setcoreidx(sih, SI_CC_IDX);
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core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
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if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
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if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
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u32 ilp_ctr, alp_hz;
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/*
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* Enable the reg to measure the freq,
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* in case it was disabled before
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*/
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W_REG(&cc->pmu_xtalfreq,
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1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
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bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
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1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
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/* Delay for well over 4 ILP clocks */
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udelay(1000);
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/* Read the latched number of ALP ticks per 4 ILP ticks */
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ilp_ctr =
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R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
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ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
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PMU_XTALFREQ_REG_ILPCTR_MASK;
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/*
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* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
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* bit to save power
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*/
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W_REG(&cc->pmu_xtalfreq, 0);
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bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
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/* Calculate ALP frequency */
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alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
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@ -446,8 +442,5 @@ u32 si_pmu_measure_alpclk(struct si_pub *sih)
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} else
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alp_khz = 0;
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/* Return to original core */
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ai_setcoreidx(sih, origidx);
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return alp_khz;
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}
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