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MIPS: CPS: Fix MIPS_ISA_LEVEL_RAW fallout
Commit17278a91e0
("MIPS: CPS: Fix r1 .set mt assembler warning") added .set MIPS_ISA_LEVEL_RAW to silence warnings about .set mt on r1, however this can result in a MOVE being encoded as a 64-bit DADDU instruction on certain version of binutils (e.g. 2.22), and reserved instruction exceptions at runtime on 32-bit hardware. Reduce the sizes of the push/pop sections to include only instructions that are part of the MT ASE or which won't convert to 64-bit instructions after .set mips64r2/mips64r6. Reported-by: Greg Ungerer <gerg@linux-m68k.org> Fixes:17278a91e0
("MIPS: CPS: Fix r1 .set mt assembler warning") Signed-off-by: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.15 Tested-by: Greg Ungerer <gerg@linux-m68k.org> Patchwork: https://patchwork.linux-mips.org/patch/18578/
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@ -388,15 +388,16 @@ LEAF(mips_cps_boot_vpes)
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#elif defined(CONFIG_MIPS_MT)
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set mt
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/* If the core doesn't support MT then return */
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has_mt t0, 5f
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/* Enter VPE configuration state */
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set mt
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dvpe
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.set pop
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PTR_LA t1, 1f
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jr.hb t1
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nop
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@ -422,6 +423,10 @@ LEAF(mips_cps_boot_vpes)
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mtc0 t0, CP0_VPECONTROL
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ehb
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.set push
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.set MIPS_ISA_LEVEL_RAW
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.set mt
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/* Skip the VPE if its TC is not halted */
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mftc0 t0, CP0_TCHALT
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beqz t0, 2f
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@ -495,6 +500,8 @@ LEAF(mips_cps_boot_vpes)
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ehb
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evpe
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.set pop
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/* Check whether this VPE is meant to be running */
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li t0, 1
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sll t0, t0, a1
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@ -509,7 +516,7 @@ LEAF(mips_cps_boot_vpes)
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1: jr.hb t0
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nop
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2: .set pop
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2:
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#endif /* CONFIG_MIPS_MT_SMP */
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