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xtensa: fsf: drop nonexistent GPIO32 support
The toolchain for xtensa FSF core never supported GPIO32, drop it on the linux side too. Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Baruch Siach <baruch@tkos.co.il>
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@ -80,7 +80,6 @@ choice
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config XTENSA_VARIANT_FSF
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bool "fsf - default (not generic) configuration"
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select MMU
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select HAVE_XTENSA_GPIO32
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config XTENSA_VARIANT_DC232B
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bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
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@ -18,13 +18,6 @@
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#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
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#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
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/* Basic parameters of each coprocessor: */
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#define XCHAL_CP7_NAME "XTIOP"
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#define XCHAL_CP7_IDENT XTIOP
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#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
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#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
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#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
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/* Filler info for unassigned coprocessors, to simplify arrays etc: */
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#define XCHAL_NCP_SA_SIZE 0
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#define XCHAL_NCP_SA_ALIGN 1
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@ -42,6 +35,8 @@
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#define XCHAL_CP5_SA_ALIGN 1
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#define XCHAL_CP6_SA_SIZE 0
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#define XCHAL_CP6_SA_ALIGN 1
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#define XCHAL_CP7_SA_SIZE 0
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#define XCHAL_CP7_SA_ALIGN 1
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/* Save area for non-coprocessor optional and custom (TIE) state: */
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#define XCHAL_NCP_SA_SIZE 0
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