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amd-xgbe-phy: Allow certain PHY settings to be set by UEFI
Certain PHY settings need to be configurable by UEFI depending on the platform being used. Add new device tree / ACPI properties that, if present, will override the pre-determined values currently used. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Lendacky, Thomas
David S. Miller
parent
82a19035d0
commit
8fdb1a09e1
@ -16,6 +16,18 @@ Optional properties:
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0 - 1GbE and 10GbE (default)
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1 - 2.5GbE and 10GbE
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The following optional properties are represented by an array with each
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value corresponding to a particular speed. The first array value represents
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the setting for the 1GbE speed, the second value for the 2.5GbE speed and
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the third value for the 10GbE speed. All three values are required if the
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property is used.
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- amd,serdes-blwc: Baseline wandering correction enablement
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0 - Off
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1 - On
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- amd,serdes-cdr-rate: CDR rate speed selection
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- amd,serdes-pq-skew: PQ (data sampling) skew
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- amd,serdes-tx-amp: TX amplitude boost
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Example:
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xgbe_phy@e1240800 {
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compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45";
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@ -25,4 +37,8 @@ Example:
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interrupt-parent = <&gic>;
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interrupts = <0 323 4>;
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amd,speed-set = <0>;
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amd,serdes-blwc = <1>, <1>, <0>;
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amd,serdes-cdr-rate = <2>, <2>, <7>;
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amd,serdes-pq-skew = <10>, <10>, <30>;
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amd,serdes-tx-amp = <15>, <15>, <10>;
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};
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@ -88,6 +88,15 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
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#define XGBE_PHY_MASK 0xfffffff0
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#define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
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#define XGBE_PHY_BLWC_PROPERTY "amd,serdes-blwc"
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#define XGBE_PHY_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
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#define XGBE_PHY_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
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#define XGBE_PHY_TX_AMP_PROPERTY "amd,serdes-tx-amp"
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#define XGBE_PHY_SPEEDS 3
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#define XGBE_PHY_SPEED_1000 0
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#define XGBE_PHY_SPEED_2500 1
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#define XGBE_PHY_SPEED_10000 2
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#define XGBE_AN_INT_CMPLT 0x01
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#define XGBE_AN_INC_LINK 0x02
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@ -152,10 +161,10 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
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#define SIR0_STATUS_RX_READY_WIDTH 1
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#define SIR0_STATUS_TX_READY_INDEX 8
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#define SIR0_STATUS_TX_READY_WIDTH 1
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#define SIR1_SPEED_CDR_RATE_INDEX 12
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#define SIR1_SPEED_CDR_RATE_WIDTH 4
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#define SIR1_SPEED_DATARATE_INDEX 4
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#define SIR1_SPEED_DATARATE_WIDTH 2
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#define SIR1_SPEED_PI_SPD_SEL_INDEX 12
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#define SIR1_SPEED_PI_SPD_SEL_WIDTH 4
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#define SIR1_SPEED_PLLSEL_INDEX 3
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#define SIR1_SPEED_PLLSEL_WIDTH 1
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#define SIR1_SPEED_RATECHANGE_INDEX 6
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@ -165,20 +174,26 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
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#define SIR1_SPEED_WORDMODE_INDEX 0
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#define SIR1_SPEED_WORDMODE_WIDTH 3
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#define SPEED_10000_BLWC 0
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#define SPEED_10000_CDR 0x7
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#define SPEED_10000_PLL 0x1
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#define SPEED_10000_PQ 0x1e
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#define SPEED_10000_RATE 0x0
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#define SPEED_10000_TXAMP 0xa
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#define SPEED_10000_WORD 0x7
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#define SPEED_2500_BLWC 1
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#define SPEED_2500_CDR 0x2
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#define SPEED_2500_PLL 0x0
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#define SPEED_2500_PQ 0xa
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#define SPEED_2500_RATE 0x1
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#define SPEED_2500_TXAMP 0xf
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#define SPEED_2500_WORD 0x1
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#define SPEED_1000_BLWC 1
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#define SPEED_1000_CDR 0x2
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#define SPEED_1000_PLL 0x0
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#define SPEED_1000_PQ 0xa
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#define SPEED_1000_RATE 0x3
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#define SPEED_1000_TXAMP 0xf
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#define SPEED_1000_WORD 0x1
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@ -193,15 +208,6 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
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#define RXTX_REG114_PQ_REG_INDEX 9
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#define RXTX_REG114_PQ_REG_WIDTH 7
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#define RXTX_10000_BLWC 0
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#define RXTX_10000_PQ 0x1e
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#define RXTX_2500_BLWC 1
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#define RXTX_2500_PQ 0xa
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#define RXTX_1000_BLWC 1
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#define RXTX_1000_PQ 0xa
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/* Bit setting and getting macros
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* The get macro will extract the current bit field value from within
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* the variable
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@ -303,6 +309,30 @@ do { \
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XRXTX_IOWRITE((_priv), _reg, reg_val); \
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} while (0)
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static const u32 amd_xgbe_phy_serdes_blwc[] = {
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SPEED_1000_BLWC,
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SPEED_2500_BLWC,
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SPEED_10000_BLWC,
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};
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static const u32 amd_xgbe_phy_serdes_cdr_rate[] = {
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SPEED_1000_CDR,
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SPEED_2500_CDR,
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SPEED_10000_CDR,
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};
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static const u32 amd_xgbe_phy_serdes_pq_skew[] = {
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SPEED_1000_PQ,
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SPEED_2500_PQ,
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SPEED_10000_PQ,
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};
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static const u32 amd_xgbe_phy_serdes_tx_amp[] = {
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SPEED_1000_TXAMP,
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SPEED_2500_TXAMP,
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SPEED_10000_TXAMP,
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};
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enum amd_xgbe_phy_an {
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AMD_XGBE_AN_READY = 0,
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AMD_XGBE_AN_PAGE_RECEIVED,
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@ -353,6 +383,17 @@ struct amd_xgbe_phy_priv {
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unsigned int speed_set;
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/* SerDes UEFI configurable settings.
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* Switching between modes/speeds requires new values for some
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* SerDes settings. The values can be supplied as device
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* properties in array format. The first array entry is for
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* 1GbE, second for 2.5GbE and third for 10GbE
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*/
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u32 serdes_blwc[XGBE_PHY_SPEEDS];
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u32 serdes_cdr_rate[XGBE_PHY_SPEEDS];
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u32 serdes_pq_skew[XGBE_PHY_SPEEDS];
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u32 serdes_tx_amp[XGBE_PHY_SPEEDS];
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/* Auto-negotiation state machine support */
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struct mutex an_mutex;
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enum amd_xgbe_phy_an an_result;
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@ -483,12 +524,16 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
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priv->serdes_cdr_rate[XGBE_PHY_SPEED_10000]);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
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priv->serdes_tx_amp[XGBE_PHY_SPEED_10000]);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
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priv->serdes_blwc[XGBE_PHY_SPEED_10000]);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
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priv->serdes_pq_skew[XGBE_PHY_SPEED_10000]);
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amd_xgbe_phy_serdes_complete_ratechange(phydev);
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@ -531,12 +576,16 @@ static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
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priv->serdes_cdr_rate[XGBE_PHY_SPEED_2500]);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
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priv->serdes_tx_amp[XGBE_PHY_SPEED_2500]);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
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priv->serdes_blwc[XGBE_PHY_SPEED_2500]);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
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priv->serdes_pq_skew[XGBE_PHY_SPEED_2500]);
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amd_xgbe_phy_serdes_complete_ratechange(phydev);
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@ -579,12 +628,16 @@ static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,
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priv->serdes_cdr_rate[XGBE_PHY_SPEED_1000]);
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XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,
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priv->serdes_tx_amp[XGBE_PHY_SPEED_1000]);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
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priv->serdes_blwc[XGBE_PHY_SPEED_1000]);
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XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
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priv->serdes_pq_skew[XGBE_PHY_SPEED_1000]);
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amd_xgbe_phy_serdes_complete_ratechange(phydev);
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@ -1555,6 +1608,66 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
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goto err_sir1;
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}
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if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) {
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ret = device_property_read_u32_array(phy_dev,
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XGBE_PHY_BLWC_PROPERTY,
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priv->serdes_blwc,
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XGBE_PHY_SPEEDS);
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if (ret) {
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dev_err(dev, "invalid %s property\n",
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XGBE_PHY_BLWC_PROPERTY);
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goto err_sir1;
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}
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} else {
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memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc,
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sizeof(priv->serdes_blwc));
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}
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if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) {
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ret = device_property_read_u32_array(phy_dev,
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XGBE_PHY_CDR_RATE_PROPERTY,
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priv->serdes_cdr_rate,
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XGBE_PHY_SPEEDS);
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if (ret) {
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dev_err(dev, "invalid %s property\n",
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XGBE_PHY_CDR_RATE_PROPERTY);
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goto err_sir1;
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}
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} else {
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memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate,
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sizeof(priv->serdes_cdr_rate));
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}
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if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) {
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ret = device_property_read_u32_array(phy_dev,
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XGBE_PHY_PQ_SKEW_PROPERTY,
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priv->serdes_pq_skew,
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XGBE_PHY_SPEEDS);
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if (ret) {
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dev_err(dev, "invalid %s property\n",
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XGBE_PHY_PQ_SKEW_PROPERTY);
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goto err_sir1;
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}
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} else {
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memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew,
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sizeof(priv->serdes_pq_skew));
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}
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if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) {
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ret = device_property_read_u32_array(phy_dev,
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XGBE_PHY_TX_AMP_PROPERTY,
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priv->serdes_tx_amp,
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XGBE_PHY_SPEEDS);
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if (ret) {
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dev_err(dev, "invalid %s property\n",
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XGBE_PHY_TX_AMP_PROPERTY);
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goto err_sir1;
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}
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} else {
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memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp,
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sizeof(priv->serdes_tx_amp));
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}
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phydev->priv = priv;
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if (!priv->adev || acpi_disabled)
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