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[ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2)
(20072fd0c9 lost most of its changes
somehow, came from a mbox archive applied with git-am. No idea
what happened. This puts back the missing bits. --rmk)
The initial patch from Lothar, and Lennert make it into a cleaner
one, modified and tested on PXA320 by Eric Miao.
This patch moves the L2 cache operations out of proc-xsc3.S into
dedicated outer cache support code.
CACHE_XSC3L2 can be deselected so no L2 cache specific code will be
linked in, and that L2 enable bit will not be set, this applies to
the following cases:
a. _only_ PXA300/PXA310 support included and no L2 cache wanted
b. PXA320 support included, but want L2 be disabled
So the enabling of L2 depends on two things:
- CACHE_XSC3L2 is selected
- and L2 cache is present
Where the latter is only a safeguard (previous testing shows it works
OK even when this bit is turned on).
IXP series of processors with XScale3 cannot disable L2 cache for the
moment since they depend on the L2 cache for its coherent memory, so
IXP may always select CACHE_XSC3L2.
Other L2 relevant bits are always turned on (i.e. the original code
enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side
effects. Specifically, these bits are:
- OC bits in TTBASE register (table walk outer cache attributes)
- LLR Outer Cache Attributes (OC) in Auxiliary Control Register
Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao
Russell King
parent
e76e3ac69e
commit
905a09d57a
@ -742,3 +742,11 @@ config CACHE_L2X0
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select OUTER_CACHE
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help
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This option enables the L2x0 PrimeCell.
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config CACHE_XSC3L2
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bool "Enable the L2 cache on XScale3"
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depends on CPU_XSC3
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default y
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select OUTER_CACHE
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help
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This option enables the L2 cache on XScale3.
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182
arch/arm/mm/cache-xsc3l2.c
Normal file
182
arch/arm/mm/cache-xsc3l2.c
Normal file
@ -0,0 +1,182 @@
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/*
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* arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
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*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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#define CR_L2 (1 << 26)
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#define CACHE_LINE_SIZE 32
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#define CACHE_LINE_SHIFT 5
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#define CACHE_WAY_PER_SET 8
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#define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
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#define CACHE_SET_SIZE(l2ctype) (CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
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static inline int xsc3_l2_present(void)
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{
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unsigned long l2ctype;
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__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
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return !!(l2ctype & 0xf8);
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}
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static inline void xsc3_l2_clean_mva(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr));
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}
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static inline void xsc3_l2_clean_pa(unsigned long addr)
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{
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xsc3_l2_clean_mva(__phys_to_virt(addr));
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}
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static inline void xsc3_l2_inv_mva(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr));
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}
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static inline void xsc3_l2_inv_pa(unsigned long addr)
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{
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xsc3_l2_inv_mva(__phys_to_virt(addr));
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}
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static inline void xsc3_l2_inv_all(void)
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{
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unsigned long l2ctype, set_way;
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int set, way;
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__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
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for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
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for (way = 0; way < CACHE_WAY_PER_SET; way++) {
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set_way = (way << 29) | (set << 5);
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__asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way));
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}
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}
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dsb();
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}
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static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
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{
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if (start == 0 && end == -1ul) {
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xsc3_l2_inv_all();
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return;
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}
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/*
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* Clean and invalidate partial first cache line.
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*/
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if (start & (CACHE_LINE_SIZE - 1)) {
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xsc3_l2_clean_pa(start & ~(CACHE_LINE_SIZE - 1));
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xsc3_l2_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
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start = (start | (CACHE_LINE_SIZE - 1)) + 1;
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}
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/*
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* Clean and invalidate partial last cache line.
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*/
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if (end & (CACHE_LINE_SIZE - 1)) {
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xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1));
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xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
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end &= ~(CACHE_LINE_SIZE - 1);
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}
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/*
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* Invalidate all full cache lines between 'start' and 'end'.
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*/
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while (start != end) {
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xsc3_l2_inv_pa(start);
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start += CACHE_LINE_SIZE;
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}
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dsb();
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}
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static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
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{
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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xsc3_l2_clean_pa(start);
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start += CACHE_LINE_SIZE;
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}
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dsb();
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}
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/*
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* optimize L2 flush all operation by set/way format
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*/
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static inline void xsc3_l2_flush_all(void)
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{
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unsigned long l2ctype, set_way;
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int set, way;
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__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
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for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
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for (way = 0; way < CACHE_WAY_PER_SET; way++) {
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set_way = (way << 29) | (set << 5);
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__asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way));
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}
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}
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dsb();
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}
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static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
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{
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if (start == 0 && end == -1ul) {
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xsc3_l2_flush_all();
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return;
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}
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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xsc3_l2_clean_pa(start);
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xsc3_l2_inv_pa(start);
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start += CACHE_LINE_SIZE;
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}
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dsb();
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}
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static int __init xsc3_l2_init(void)
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{
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if (!cpu_is_xsc3() || !xsc3_l2_present())
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return 0;
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if (!(get_cr() & CR_L2)) {
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pr_info("XScale3 L2 cache enabled.\n");
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adjust_cr(CR_L2, CR_L2);
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xsc3_l2_inv_all();
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}
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outer_cache.inv_range = xsc3_l2_inv_range;
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outer_cache.clean_range = xsc3_l2_clean_range;
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outer_cache.flush_range = xsc3_l2_flush_range;
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return 0;
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}
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core_initcall(xsc3_l2_init);
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@ -51,11 +51,6 @@
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*/
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#define CACHESIZE 32768
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/*
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* Run with L2 enabled.
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*/
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#define L2_CACHE_ENABLE 1
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/*
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* This macro is used to wait for a CP15 write and is needed when we
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* have to ensure that the last operation to the coprocessor was
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@ -265,12 +260,9 @@ ENTRY(xsc3_dma_inv_range)
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tst r0, #CACHELINESIZE - 1
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bic r0, r0, #CACHELINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcrne p15, 1, r0, c7, c11, 1 @ clean L2 line
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tst r1, #CACHELINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
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mcrne p15, 1, r1, c7, c11, 1 @ clean L2 line
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
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mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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@ -288,7 +280,6 @@ ENTRY(xsc3_dma_inv_range)
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ENTRY(xsc3_dma_clean_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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@ -306,8 +297,6 @@ ENTRY(xsc3_dma_clean_range)
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ENTRY(xsc3_dma_flush_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
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mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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@ -347,9 +336,7 @@ ENTRY(cpu_xsc3_switch_mm)
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mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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#ifdef L2_CACHE_ENABLE
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orr r0, r0, #0x18 @ cache the page table in L2
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#endif
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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cpwait_ret lr, ip
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@ -378,12 +365,10 @@ ENTRY(cpu_xsc3_set_pte_ext)
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orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
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@ combined with user -> user r/w
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#if L2_CACHE_ENABLE
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@ If it's cacheable, it needs to be in L2 also.
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eor ip, r1, #L_PTE_CACHEABLE
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tst ip, #L_PTE_CACHEABLE
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orreq r2, r2, #PTE_EXT_TEX(0x5)
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#endif
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
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movne r2, #0 @ no -> fault
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@ -408,9 +393,7 @@ __xsc3_setup:
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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#if L2_CACHE_ENABLE
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orr r4, r4, #0x18 @ cache the page table in L2
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#endif
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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mov r0, #0 @ don't allow CP access
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@ -418,9 +401,7 @@ __xsc3_setup:
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mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
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and r0, r0, #2 @ preserve bit P bit setting
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#if L2_CACHE_ENABLE
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orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
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#endif
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mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
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adr r5, xsc3_crval
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@ -429,9 +410,6 @@ __xsc3_setup:
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bic r0, r0, r5 @ ..V. ..R. .... ..A.
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orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
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@ ...I Z..S .... .... (uc)
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#if L2_CACHE_ENABLE
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orr r0, r0, #0x04000000 @ L2 enable
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#endif
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mov pc, lr
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.size __xsc3_setup, . - __xsc3_setup
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