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tools/power/turbostat: split core MSR support into status + limit

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Some CPUs may not have PP0/Core domain power limit MSRs. We
should still allow its domain energy status to be used. This
patch splits PP0/Core RAPL into two separate flags for power
limit and energy status such that energy status can continue
to be reported without power limit.

Without this patch, turbostat will not be able to use the
remaining RAPL features if some PL MSRs are not present.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Jacob Pan 2016-06-16 09:48:20 -07:00 committed by Len Brown
parent 0a91e55152
commit 9148494c59
1 changed files with 11 additions and 9 deletions
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20
tools/power/x86/turbostat/turbostat.c
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@ -129,9 +129,8 @@ unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
#define RAPL_DRAM_POWER_INFO (1 << 5) #define RAPL_DRAM_POWER_INFO (1 << 5)
/* 0x61c MSR_DRAM_POWER_INFO */ /* 0x61c MSR_DRAM_POWER_INFO */
#define RAPL_CORES (1 << 6) #define RAPL_CORES_POWER_LIMIT (1 << 6)
/* 0x638 MSR_PP0_POWER_LIMIT */ /* 0x638 MSR_PP0_POWER_LIMIT */
/* 0x639 MSR_PP0_ENERGY_STATUS */
#define RAPL_CORE_POLICY (1 << 7) #define RAPL_CORE_POLICY (1 << 7)
/* 0x63a MSR_PP0_POLICY */ /* 0x63a MSR_PP0_POLICY */
@ -139,6 +138,10 @@ unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
/* 0x640 MSR_PP1_POWER_LIMIT */ /* 0x640 MSR_PP1_POWER_LIMIT */
/* 0x641 MSR_PP1_ENERGY_STATUS */ /* 0x641 MSR_PP1_ENERGY_STATUS */
/* 0x642 MSR_PP1_POLICY */ /* 0x642 MSR_PP1_POLICY */
#define RAPL_CORES_ENERGY_STATUS (1 << 9)
/* 0x639 MSR_PP0_ENERGY_STATUS */
#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
#define TJMAX_DEFAULT 100 #define TJMAX_DEFAULT 100
#define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MAX(a, b) ((a) > (b) ? (a) : (b))
@ -397,7 +400,7 @@ void print_header(void)
if (do_rapl && !rapl_joules) { if (do_rapl && !rapl_joules) {
if (do_rapl & RAPL_PKG) if (do_rapl & RAPL_PKG)
outp += sprintf(outp, "\tPkgWatt"); outp += sprintf(outp, "\tPkgWatt");
if (do_rapl & RAPL_CORES) if (do_rapl & RAPL_CORES_ENERGY_STATUS)
outp += sprintf(outp, "\tCorWatt"); outp += sprintf(outp, "\tCorWatt");
if (do_rapl & RAPL_GFX) if (do_rapl & RAPL_GFX)
outp += sprintf(outp, "\tGFXWatt"); outp += sprintf(outp, "\tGFXWatt");
@ -410,7 +413,7 @@ void print_header(void)
} else if (do_rapl && rapl_joules) { } else if (do_rapl && rapl_joules) {
if (do_rapl & RAPL_PKG) if (do_rapl & RAPL_PKG)
outp += sprintf(outp, "\tPkg_J"); outp += sprintf(outp, "\tPkg_J");
if (do_rapl & RAPL_CORES) if (do_rapl & RAPL_CORES_ENERGY_STATUS)
outp += sprintf(outp, "\tCor_J"); outp += sprintf(outp, "\tCor_J");
if (do_rapl & RAPL_GFX) if (do_rapl & RAPL_GFX)
outp += sprintf(outp, "\tGFX_J"); outp += sprintf(outp, "\tGFX_J");
@ -657,7 +660,7 @@ int format_counters(struct thread_data *t, struct core_data *c,
if (do_rapl && !rapl_joules) { if (do_rapl && !rapl_joules) {
if (do_rapl & RAPL_PKG) if (do_rapl & RAPL_PKG)
outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
if (do_rapl & RAPL_CORES) if (do_rapl & RAPL_CORES_ENERGY_STATUS)
outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
if (do_rapl & RAPL_GFX) if (do_rapl & RAPL_GFX)
outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
@ -1217,7 +1220,7 @@ retry:
return -13; return -13;
p->energy_pkg = msr & 0xFFFFFFFF; p->energy_pkg = msr & 0xFFFFFFFF;
} }
if (do_rapl & RAPL_CORES) { if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
return -14; return -14;
p->energy_cores = msr & 0xFFFFFFFF; p->energy_cores = msr & 0xFFFFFFFF;
@ -2657,7 +2660,7 @@ void rapl_probe(unsigned int family, unsigned int model)
break; break;
case 0x37: /* BYT */ case 0x37: /* BYT */
case 0x4D: /* AVN */ case 0x4D: /* AVN */
do_rapl = RAPL_PKG | RAPL_CORES ; do_rapl = RAPL_PKG | RAPL_CORES;
break; break;
default: default:
return; return;
@ -2872,9 +2875,8 @@ int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
} }
} }
if (do_rapl & RAPL_CORES) { if (do_rapl & RAPL_CORES_POWER_LIMIT) {
if (debug) { if (debug) {
if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
return -9; return -9;
fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",