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powerpc/mm: Convert 4k hash insert to C
Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
17ed9e3192
commit
91f1da9979
@ -18,6 +18,9 @@ obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
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obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
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tlb_hash$(CONFIG_WORD_SIZE).o \
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mmu_context_hash$(CONFIG_WORD_SIZE).o
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ifeq ($(CONFIG_PPC_STD_MMU_64),y)
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obj-$(CONFIG_PPC_64K_PAGES) += hash64_64k.o
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endif
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obj-$(CONFIG_PPC_ICSWX) += icswx.o
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obj-$(CONFIG_PPC_ICSWX_PID) += icswx_pid.o
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obj-$(CONFIG_40x) += 40x_mmu.o
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202
arch/powerpc/mm/hash64_64k.c
Normal file
202
arch/powerpc/mm/hash64_64k.c
Normal file
@ -0,0 +1,202 @@
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/*
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* Copyright IBM Corporation, 2015
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU Lesser General Public License
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#include <linux/mm.h>
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#include <asm/machdep.h>
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#include <asm/mmu.h>
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int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
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pte_t *ptep, unsigned long trap, unsigned long flags,
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int ssize, int subpg_prot)
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{
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real_pte_t rpte;
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unsigned long *hidxp;
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unsigned long hpte_group;
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unsigned int subpg_index;
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unsigned long rflags, pa, hidx;
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unsigned long old_pte, new_pte, subpg_pte;
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unsigned long vpn, hash, slot;
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unsigned long shift = mmu_psize_defs[MMU_PAGE_4K].shift;
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/*
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* atomically mark the linux large page PTE busy and dirty
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*/
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do {
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pte_t pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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/* If PTE busy, retry the access */
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if (unlikely(old_pte & _PAGE_BUSY))
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return 0;
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/* If PTE permissions don't match, take page fault */
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if (unlikely(access & ~old_pte))
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return 1;
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/*
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* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access. Since this is 4K insert of 64K page size
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* also add _PAGE_COMBO
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*/
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new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED | _PAGE_COMBO;
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if (access & _PAGE_RW)
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new_pte |= _PAGE_DIRTY;
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} while (old_pte != __cmpxchg_u64((unsigned long *)ptep,
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old_pte, new_pte));
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/*
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* Handle the subpage protection bits
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*/
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subpg_pte = new_pte & ~subpg_prot;
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/*
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* PP bits. _PAGE_USER is already PP bit 0x2, so we only
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* need to add in 0x1 if it's a read-only user page
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*/
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rflags = subpg_pte & _PAGE_USER;
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if ((subpg_pte & _PAGE_USER) && !((subpg_pte & _PAGE_RW) &&
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(subpg_pte & _PAGE_DIRTY)))
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rflags |= 0x1;
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/*
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* _PAGE_EXEC -> HW_NO_EXEC since it's inverted
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*/
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rflags |= ((subpg_pte & _PAGE_EXEC) ? 0 : HPTE_R_N);
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/*
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* Always add C and Memory coherence bit
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*/
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rflags |= HPTE_R_C | HPTE_R_M;
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/*
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* Add in WIMG bits
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*/
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rflags |= (subpg_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
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_PAGE_COHERENT | _PAGE_GUARDED));
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if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
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!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
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/*
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* No CPU has hugepages but lacks no execute, so we
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* don't need to worry about that case
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*/
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
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}
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subpg_index = (ea & (PAGE_SIZE - 1)) >> shift;
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vpn = hpt_vpn(ea, vsid, ssize);
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rpte = __real_pte(__pte(old_pte), ptep);
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/*
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*None of the sub 4k page is hashed
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*/
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if (!(old_pte & _PAGE_HASHPTE))
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goto htab_insert_hpte;
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/*
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* Check if the pte was already inserted into the hash table
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* as a 64k HW page, and invalidate the 64k HPTE if so.
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*/
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if (!(old_pte & _PAGE_COMBO)) {
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flush_hash_page(vpn, rpte, MMU_PAGE_64K, ssize, flags);
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old_pte &= ~_PAGE_HPTE_SUB;
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goto htab_insert_hpte;
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}
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/*
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* Check for sub page valid and update
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*/
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if (__rpte_sub_valid(rpte, subpg_index)) {
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int ret;
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hash = hpt_hash(vpn, shift, ssize);
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hidx = __rpte_to_hidx(rpte, subpg_index);
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if (hidx & _PTEIDX_SECONDARY)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += hidx & _PTEIDX_GROUP_IX;
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ret = ppc_md.hpte_updatepp(slot, rflags, vpn,
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MMU_PAGE_4K, MMU_PAGE_4K,
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ssize, flags);
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/*
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*if we failed because typically the HPTE wasn't really here
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* we try an insertion.
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*/
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if (ret == -1)
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goto htab_insert_hpte;
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*ptep = __pte(new_pte & ~_PAGE_BUSY);
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return 0;
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}
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htab_insert_hpte:
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/*
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* handle _PAGE_4K_PFN case
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*/
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if (old_pte & _PAGE_4K_PFN) {
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/*
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* All the sub 4k page have the same
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* physical address.
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*/
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pa = pte_pfn(__pte(old_pte)) << HW_PAGE_SHIFT;
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} else {
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pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
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pa += (subpg_index << shift);
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}
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hash = hpt_hash(vpn, shift, ssize);
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repeat:
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hpte_group = ((hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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/* Insert into the hash table, primary slot */
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slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
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MMU_PAGE_4K, MMU_PAGE_4K, ssize);
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/*
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* Primary is full, try the secondary
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*/
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if (unlikely(slot == -1)) {
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hpte_group = ((~hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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slot = ppc_md.hpte_insert(hpte_group, vpn, pa,
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rflags, HPTE_V_SECONDARY,
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MMU_PAGE_4K, MMU_PAGE_4K, ssize);
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if (slot == -1) {
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if (mftb() & 0x1)
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hpte_group = ((hash & htab_hash_mask) *
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HPTES_PER_GROUP) & ~0x7UL;
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ppc_md.hpte_remove(hpte_group);
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/*
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* FIXME!! Should be try the group from which we removed ?
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*/
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goto repeat;
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}
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}
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/*
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* Hypervisor failure. Restore old pmd and return -1
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* similar to __hash_page_*
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*/
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if (unlikely(slot == -2)) {
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*ptep = __pte(old_pte);
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hash_failure_debug(ea, access, vsid, trap, ssize,
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MMU_PAGE_4K, MMU_PAGE_4K, old_pte);
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return -1;
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}
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/*
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* Insert slot number & secondary bit in PTE second half,
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* clear _PAGE_BUSY and set appropriate HPTE slot bit
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* Since we have _PAGE_BUSY set on ptep, we can be sure
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* nobody is undating hidx.
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*/
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hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);
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/* __real_pte use pte_val() any idea why ? FIXME!! */
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rpte.hidx &= ~(0xfUL << (subpg_index << 2));
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*hidxp = rpte.hidx | (slot << (subpg_index << 2));
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new_pte |= (_PAGE_HPTE_SUB0 >> subpg_index);
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/*
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* check __real_pte for details on matching smp_rmb()
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*/
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smp_wmb();
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*ptep = __pte(new_pte & ~_PAGE_BUSY);
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return 0;
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}
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@ -328,381 +328,8 @@ htab_pte_insert_failure:
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li r3,-1
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b htab_bail
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#else /* CONFIG_PPC_64K_PAGES */
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/*****************************************************************************
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* *
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* 64K SW & 4K or 64K HW in a 4K segment pages implementation *
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* *
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*****************************************************************************/
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/* _hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
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* pte_t *ptep, unsigned long trap, unsigned local flags,
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* int ssize, int subpg_prot)
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*/
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/*
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* For now, we do NOT implement Admixed pages
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*/
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_GLOBAL(__hash_page_4K)
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mflr r0
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std r0,16(r1)
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stdu r1,-STACKFRAMESIZE(r1)
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/* Save all params that we need after a function call */
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std r6,STK_PARAM(R6)(r1)
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std r8,STK_PARAM(R8)(r1)
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std r9,STK_PARAM(R9)(r1)
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/* Save non-volatile registers.
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* r31 will hold "old PTE"
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* r30 is "new PTE"
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* r29 is vpn
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* r28 is a hash value
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* r27 is hashtab mask (maybe dynamic patched instead ?)
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* r26 is the hidx mask
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* r25 is the index in combo page
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*/
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std r25,STK_REG(R25)(r1)
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std r26,STK_REG(R26)(r1)
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std r27,STK_REG(R27)(r1)
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std r28,STK_REG(R28)(r1)
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std r29,STK_REG(R29)(r1)
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std r30,STK_REG(R30)(r1)
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std r31,STK_REG(R31)(r1)
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/* Step 1:
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*
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* Check permissions, atomically mark the linux PTE busy
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* and hashed.
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*/
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1:
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ldarx r31,0,r6
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/* Check access rights (access & ~(pte_val(*ptep))) */
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andc. r0,r4,r31
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bne- htab_wrong_access
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/* Check if PTE is busy */
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andi. r0,r31,_PAGE_BUSY
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/* If so, just bail out and refault if needed. Someone else
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* is changing this PTE anyway and might hash it.
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*/
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bne- htab_bail_ok
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/* Prepare new PTE value (turn access RW into DIRTY, then
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* add BUSY and ACCESSED)
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*/
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rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
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or r30,r30,r31
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ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED
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oris r30,r30,_PAGE_COMBO@h
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/* Write the linux PTE atomically (setting busy) */
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stdcx. r30,0,r6
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bne- 1b
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isync
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/* Step 2:
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*
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* Insert/Update the HPTE in the hash table. At this point,
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* r4 (access) is re-useable, we use it for the new HPTE flags
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*/
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/* Load the hidx index */
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rldicl r25,r3,64-12,60
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BEGIN_FTR_SECTION
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cmpdi r9,0 /* check segment size */
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bne 3f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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/* Calc vpn and put it in r29 */
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sldi r29,r5,SID_SHIFT - VPN_SHIFT
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/*
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* clrldi r3,r3,64 - SID_SHIFT --> ea & 0xfffffff
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* srdi r28,r3,VPN_SHIFT
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*/
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rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
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or r29,r28,r29
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/*
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* Calculate hash value for primary slot and store it in r28
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* r3 = va, r5 = vsid
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* r0 = (va >> 12) & ((1ul << (28 - 12)) -1)
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*/
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rldicl r0,r3,64-12,48
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xor r28,r5,r0 /* hash */
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b 4f
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3: /* Calc vpn and put it in r29 */
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sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
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/*
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* clrldi r3,r3,64 - SID_SHIFT_1T --> ea & 0xffffffffff
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* srdi r28,r3,VPN_SHIFT
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*/
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rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
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or r29,r28,r29
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/*
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* Calculate hash value for primary slot and
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* store it in r28 for 1T segment
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* r3 = va, r5 = vsid
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*/
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sldi r28,r5,25 /* vsid << 25 */
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/* r0 = (va >> 12) & ((1ul << (40 - 12)) -1) */
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rldicl r0,r3,64-12,36
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xor r28,r28,r5 /* vsid ^ ( vsid << 25) */
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xor r28,r28,r0 /* hash */
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/* Convert linux PTE bits into HW equivalents */
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4:
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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andc r10,r30,r10
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andi. r3,r10,0x1fe /* Get basic set of flags */
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rlwinm r0,r10,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
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#else
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andi. r3,r30,0x1fe /* Get basic set of flags */
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rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
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#endif
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xori r3,r3,HPTE_R_N /* _PAGE_EXEC -> NOEXEC */
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rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
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and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
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andc r0,r3,r0 /* r0 = pte & ~r0 */
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rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
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/*
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* Always add "C" bit for perf. Memory coherence is always enabled
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*/
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ori r3,r3,HPTE_R_C | HPTE_R_M
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/* We eventually do the icache sync here (maybe inline that
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* code rather than call a C function...)
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*/
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BEGIN_FTR_SECTION
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mr r4,r30
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mr r5,r7
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bl hash_page_do_lazy_icache
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END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
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/* At this point, r3 contains new PP bits, save them in
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* place of "access" in the param area (sic)
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*/
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std r3,STK_PARAM(R4)(r1)
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/* Get htab_hash_mask */
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ld r4,htab_hash_mask@got(2)
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ld r27,0(r4) /* htab_hash_mask -> r27 */
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/* Check if we may already be in the hashtable, in this case, we
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* go to out-of-line code to try to modify the HPTE. We look for
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* the bit at (1 >> (index + 32))
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*/
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rldicl. r0,r31,64-12,48
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li r26,0 /* Default hidx */
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beq htab_insert_pte
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/*
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* Check if the pte was already inserted into the hash table
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* as a 64k HW page, and invalidate the 64k HPTE if so.
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*/
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andis. r0,r31,_PAGE_COMBO@h
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beq htab_inval_old_hpte
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ld r6,STK_PARAM(R6)(r1)
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ori r26,r6,PTE_PAGE_HIDX_OFFSET /* Load the hidx mask. */
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ld r26,0(r26)
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addi r5,r25,36 /* Check actual HPTE_SUB bit, this */
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rldcr. r0,r31,r5,0 /* must match pgtable.h definition */
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bne htab_modify_pte
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htab_insert_pte:
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/* real page number in r5, PTE RPN value + index */
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andis. r0,r31,_PAGE_4K_PFN@h
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srdi r5,r31,PTE_RPN_SHIFT
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bne- htab_special_pfn
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sldi r5,r5,PAGE_FACTOR
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add r5,r5,r25
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htab_special_pfn:
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sldi r5,r5,HW_PAGE_SHIFT
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/* Calculate primary group hash */
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and r0,r28,r27
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rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
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/* Call ppc_md.hpte_insert */
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ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
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mr r4,r29 /* Retrieve vpn */
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li r7,0 /* !bolted, !secondary */
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li r8,MMU_PAGE_4K /* page size */
|
||||
li r9,MMU_PAGE_4K /* actual page size */
|
||||
ld r10,STK_PARAM(R9)(r1) /* segment size */
|
||||
.globl htab_call_hpte_insert1
|
||||
htab_call_hpte_insert1:
|
||||
bl . /* patched by htab_finish_init() */
|
||||
cmpdi 0,r3,0
|
||||
bge htab_pte_insert_ok /* Insertion successful */
|
||||
cmpdi 0,r3,-2 /* Critical failure */
|
||||
beq- htab_pte_insert_failure
|
||||
|
||||
/* Now try secondary slot */
|
||||
|
||||
/* real page number in r5, PTE RPN value + index */
|
||||
andis. r0,r31,_PAGE_4K_PFN@h
|
||||
srdi r5,r31,PTE_RPN_SHIFT
|
||||
bne- 3f
|
||||
sldi r5,r5,PAGE_FACTOR
|
||||
add r5,r5,r25
|
||||
3: sldi r5,r5,HW_PAGE_SHIFT
|
||||
|
||||
/* Calculate secondary group hash */
|
||||
andc r0,r27,r28
|
||||
rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
|
||||
|
||||
/* Call ppc_md.hpte_insert */
|
||||
ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
|
||||
mr r4,r29 /* Retrieve vpn */
|
||||
li r7,HPTE_V_SECONDARY /* !bolted, secondary */
|
||||
li r8,MMU_PAGE_4K /* page size */
|
||||
li r9,MMU_PAGE_4K /* actual page size */
|
||||
ld r10,STK_PARAM(R9)(r1) /* segment size */
|
||||
.globl htab_call_hpte_insert2
|
||||
htab_call_hpte_insert2:
|
||||
bl . /* patched by htab_finish_init() */
|
||||
cmpdi 0,r3,0
|
||||
bge+ htab_pte_insert_ok /* Insertion successful */
|
||||
cmpdi 0,r3,-2 /* Critical failure */
|
||||
beq- htab_pte_insert_failure
|
||||
|
||||
/* Both are full, we need to evict something */
|
||||
mftb r0
|
||||
/* Pick a random group based on TB */
|
||||
andi. r0,r0,1
|
||||
mr r5,r28
|
||||
bne 2f
|
||||
not r5,r5
|
||||
2: and r0,r5,r27
|
||||
rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
|
||||
/* Call ppc_md.hpte_remove */
|
||||
.globl htab_call_hpte_remove
|
||||
htab_call_hpte_remove:
|
||||
bl . /* patched by htab_finish_init() */
|
||||
|
||||
/* Try all again */
|
||||
b htab_insert_pte
|
||||
|
||||
/*
|
||||
* Call out to C code to invalidate an 64k HW HPTE that is
|
||||
* useless now that the segment has been switched to 4k pages.
|
||||
*/
|
||||
htab_inval_old_hpte:
|
||||
mr r3,r29 /* vpn */
|
||||
mr r4,r31 /* PTE.pte */
|
||||
li r5,0 /* PTE.hidx */
|
||||
li r6,MMU_PAGE_64K /* psize */
|
||||
ld r7,STK_PARAM(R9)(r1) /* ssize */
|
||||
ld r8,STK_PARAM(R8)(r1) /* flags */
|
||||
bl flush_hash_page
|
||||
/* Clear out _PAGE_HPTE_SUB bits in the new linux PTE */
|
||||
lis r0,_PAGE_HPTE_SUB@h
|
||||
ori r0,r0,_PAGE_HPTE_SUB@l
|
||||
andc r30,r30,r0
|
||||
b htab_insert_pte
|
||||
|
||||
htab_bail_ok:
|
||||
li r3,0
|
||||
b htab_bail
|
||||
|
||||
htab_pte_insert_ok:
|
||||
/* Insert slot number & secondary bit in PTE second half,
|
||||
* clear _PAGE_BUSY and set approriate HPTE slot bit
|
||||
*/
|
||||
ld r6,STK_PARAM(R6)(r1)
|
||||
li r0,_PAGE_BUSY
|
||||
andc r30,r30,r0
|
||||
/* HPTE SUB bit */
|
||||
li r0,1
|
||||
subfic r5,r25,27 /* Must match bit position in */
|
||||
sld r0,r0,r5 /* pgtable.h */
|
||||
or r30,r30,r0
|
||||
/* hindx */
|
||||
sldi r5,r25,2
|
||||
sld r3,r3,r5
|
||||
li r4,0xf
|
||||
sld r4,r4,r5
|
||||
andc r26,r26,r4
|
||||
or r26,r26,r3
|
||||
ori r5,r6,PTE_PAGE_HIDX_OFFSET
|
||||
std r26,0(r5)
|
||||
lwsync
|
||||
std r30,0(r6)
|
||||
li r3, 0
|
||||
htab_bail:
|
||||
ld r25,STK_REG(R25)(r1)
|
||||
ld r26,STK_REG(R26)(r1)
|
||||
ld r27,STK_REG(R27)(r1)
|
||||
ld r28,STK_REG(R28)(r1)
|
||||
ld r29,STK_REG(R29)(r1)
|
||||
ld r30,STK_REG(R30)(r1)
|
||||
ld r31,STK_REG(R31)(r1)
|
||||
addi r1,r1,STACKFRAMESIZE
|
||||
ld r0,16(r1)
|
||||
mtlr r0
|
||||
blr
|
||||
|
||||
htab_modify_pte:
|
||||
/* Keep PP bits in r4 and slot idx from the PTE around in r3 */
|
||||
mr r4,r3
|
||||
sldi r5,r25,2
|
||||
srd r3,r26,r5
|
||||
|
||||
/* Secondary group ? if yes, get a inverted hash value */
|
||||
mr r5,r28
|
||||
andi. r0,r3,0x8 /* page secondary ? */
|
||||
beq 1f
|
||||
not r5,r5
|
||||
1: andi. r3,r3,0x7 /* extract idx alone */
|
||||
|
||||
/* Calculate proper slot value for ppc_md.hpte_updatepp */
|
||||
and r0,r5,r27
|
||||
rldicr r0,r0,3,63-3 /* r0 = (hash & mask) << 3 */
|
||||
add r3,r0,r3 /* add slot idx */
|
||||
|
||||
/* Call ppc_md.hpte_updatepp */
|
||||
mr r5,r29 /* vpn */
|
||||
li r6,MMU_PAGE_4K /* base page size */
|
||||
li r7,MMU_PAGE_4K /* actual page size */
|
||||
ld r8,STK_PARAM(R9)(r1) /* segment size */
|
||||
ld r9,STK_PARAM(R8)(r1) /* get "flags" param */
|
||||
.globl htab_call_hpte_updatepp
|
||||
htab_call_hpte_updatepp:
|
||||
bl . /* patched by htab_finish_init() */
|
||||
|
||||
/* if we failed because typically the HPTE wasn't really here
|
||||
* we try an insertion.
|
||||
*/
|
||||
cmpdi 0,r3,-1
|
||||
beq- htab_insert_pte
|
||||
|
||||
/* Clear the BUSY bit and Write out the PTE */
|
||||
li r0,_PAGE_BUSY
|
||||
andc r30,r30,r0
|
||||
ld r6,STK_PARAM(R6)(r1)
|
||||
std r30,0(r6)
|
||||
li r3,0
|
||||
b htab_bail
|
||||
|
||||
htab_wrong_access:
|
||||
/* Bail out clearing reservation */
|
||||
stdcx. r31,0,r6
|
||||
li r3,1
|
||||
b htab_bail
|
||||
|
||||
htab_pte_insert_failure:
|
||||
/* Bail out restoring old PTE */
|
||||
ld r6,STK_PARAM(R6)(r1)
|
||||
std r31,0(r6)
|
||||
li r3,-1
|
||||
b htab_bail
|
||||
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
|
||||
#ifdef CONFIG_PPC_64K_PAGES
|
||||
|
||||
/*****************************************************************************
|
||||
* *
|
||||
* 64K SW & 64K HW in a 64K segment pages implementation *
|
||||
@ -994,10 +621,3 @@ ht64_pte_insert_failure:
|
||||
|
||||
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* *
|
||||
* Huge pages implementation is in hugetlbpage.c *
|
||||
* *
|
||||
*****************************************************************************/
|
||||
|
||||
@ -653,7 +653,7 @@ static void __init htab_finish_init(void)
|
||||
patch_branch(ht64_call_hpte_updatepp,
|
||||
ppc_function_entry(ppc_md.hpte_updatepp),
|
||||
BRANCH_SET_LINK);
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
#else /* !CONFIG_PPC_64K_PAGES */
|
||||
|
||||
patch_branch(htab_call_hpte_insert1,
|
||||
ppc_function_entry(ppc_md.hpte_insert),
|
||||
@ -667,6 +667,8 @@ static void __init htab_finish_init(void)
|
||||
patch_branch(htab_call_hpte_updatepp,
|
||||
ppc_function_entry(ppc_md.hpte_updatepp),
|
||||
BRANCH_SET_LINK);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static void __init htab_initialize(void)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user