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MIPS: 74K/1074K: Correct erratum workaround.
Make sure 74K revision numbers are not applied to the 1074K. Also catch invalid usage. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5857/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -786,20 +786,30 @@ static inline void rm7k_erratum31(void)
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static inline void alias_74k_erratum(struct cpuinfo_mips *c)
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{
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unsigned int imp = c->processor_id & PRID_IMP_MASK;
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unsigned int rev = c->processor_id & PRID_REV_MASK;
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/*
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* Early versions of the 74K do not update the cache tags on a
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* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
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* aliases. In this case it is better to treat the cache as always
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* having aliases.
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*/
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if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(2, 4, 0))
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c->dcache.flags |= MIPS_CACHE_VTAG;
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if ((c->processor_id & PRID_REV_MASK) == PRID_REV_ENCODE_332(2, 4, 0))
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write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
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if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_1074K &&
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(c->processor_id & PRID_REV_MASK) <= PRID_REV_ENCODE_332(1, 1, 0)) {
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c->dcache.flags |= MIPS_CACHE_VTAG;
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write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
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switch (imp) {
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case PRID_IMP_74K:
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if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
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c->dcache.flags |= MIPS_CACHE_VTAG;
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if (rev == PRID_REV_ENCODE_332(2, 4, 0))
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write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
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break;
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case PRID_IMP_1074K:
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if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
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c->dcache.flags |= MIPS_CACHE_VTAG;
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write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
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}
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break;
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default:
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BUG();
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}
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}
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