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dmaengine: bcm2835: move controlblock chain generation into separate method
In preparation of adding slave_sg functionality this patch moves the generation/allocation of bcm2835_desc and the building of the corresponding DMA-control-block chain from bcm2835_dma_prep_dma_cyclic into the newly created method bcm2835_dma_create_cb_chain. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Martin Sperl
Vinod Koul
parent
a4dcdd849e
commit
92153bb534
@ -88,12 +88,12 @@ struct bcm2835_desc {
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struct virt_dma_desc vd;
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enum dma_transfer_direction dir;
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struct bcm2835_cb_entry *cb_list;
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unsigned int frames;
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size_t size;
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bool cyclic;
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struct bcm2835_cb_entry cb_list[];
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};
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#define BCM2835_DMA_CS 0x00
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@ -169,6 +169,13 @@ struct bcm2835_desc {
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#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
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#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
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/* how many frames of max_len size do we need to transfer len bytes */
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static inline size_t bcm2835_dma_frames_for_length(size_t len,
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size_t max_len)
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{
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return DIV_ROUND_UP(len, max_len);
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}
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static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
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{
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return container_of(d, struct bcm2835_dmadev, ddev);
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@ -185,19 +192,161 @@ static inline struct bcm2835_desc *to_bcm2835_dma_desc(
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return container_of(t, struct bcm2835_desc, vd.tx);
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}
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static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
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static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
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{
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struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
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int i;
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size_t i;
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for (i = 0; i < desc->frames; i++)
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dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
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desc->cb_list[i].paddr);
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kfree(desc->cb_list);
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kfree(desc);
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}
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static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
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{
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bcm2835_dma_free_cb_chain(
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container_of(vd, struct bcm2835_desc, vd));
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}
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static void bcm2835_dma_create_cb_set_length(
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struct bcm2835_chan *chan,
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struct bcm2835_dma_cb *control_block,
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size_t len,
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size_t period_len,
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size_t *total_len,
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u32 finalextrainfo)
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{
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/* set the length */
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control_block->length = len;
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/* finished if we have no period_length */
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if (!period_len)
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return;
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/*
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* period_len means: that we need to generate
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* transfers that are terminating at every
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* multiple of period_len - this is typically
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* used to set the interrupt flag in info
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* which is required during cyclic transfers
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*/
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/* have we filled in period_length yet? */
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if (*total_len + control_block->length < period_len)
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return;
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/* calculate the length that remains to reach period_length */
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control_block->length = period_len - *total_len;
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/* reset total_length for next period */
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*total_len = 0;
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/* add extrainfo bits in info */
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control_block->info |= finalextrainfo;
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}
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/**
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* bcm2835_dma_create_cb_chain - create a control block and fills data in
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*
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* @chan: the @dma_chan for which we run this
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* @direction: the direction in which we transfer
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* @cyclic: it is a cyclic transfer
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* @info: the default info bits to apply per controlblock
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* @frames: number of controlblocks to allocate
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* @src: the src address to assign (if the S_INC bit is set
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* in @info, then it gets incremented)
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* @dst: the dst address to assign (if the D_INC bit is set
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* in @info, then it gets incremented)
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* @buf_len: the full buffer length (may also be 0)
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* @period_len: the period length when to apply @finalextrainfo
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* in addition to the last transfer
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* this will also break some control-blocks early
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* @finalextrainfo: additional bits in last controlblock
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* (or when period_len is reached in case of cyclic)
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* @gfp: the GFP flag to use for allocation
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*/
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static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
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struct dma_chan *chan, enum dma_transfer_direction direction,
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bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
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dma_addr_t src, dma_addr_t dst, size_t buf_len,
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size_t period_len, gfp_t gfp)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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size_t len = buf_len, total_len;
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size_t frame;
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struct bcm2835_desc *d;
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struct bcm2835_cb_entry *cb_entry;
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struct bcm2835_dma_cb *control_block;
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/* allocate and setup the descriptor. */
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d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
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gfp);
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if (!d)
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return NULL;
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d->c = c;
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d->dir = direction;
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d->cyclic = cyclic;
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/*
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* Iterate over all frames, create a control block
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* for each frame and link them together.
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*/
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for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
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cb_entry = &d->cb_list[frame];
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cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
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&cb_entry->paddr);
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if (!cb_entry->cb)
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goto error_cb;
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/* fill in the control block */
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control_block = cb_entry->cb;
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control_block->info = info;
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control_block->src = src;
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control_block->dst = dst;
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control_block->stride = 0;
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control_block->next = 0;
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/* set up length in control_block if requested */
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if (buf_len) {
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/* calculate length honoring period_length */
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bcm2835_dma_create_cb_set_length(
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c, control_block,
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len, period_len, &total_len,
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cyclic ? finalextrainfo : 0);
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/* calculate new remaining length */
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len -= control_block->length;
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}
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/* link this the last controlblock */
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if (frame)
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d->cb_list[frame - 1].cb->next = cb_entry->paddr;
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/* update src and dst and length */
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if (src && (info & BCM2835_DMA_S_INC))
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src += control_block->length;
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if (dst && (info & BCM2835_DMA_D_INC))
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dst += control_block->length;
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/* Length of total transfer */
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d->size += control_block->length;
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}
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/* the last frame requires extra flags */
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d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
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/* detect a size missmatch */
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if (buf_len && (d->size != buf_len))
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goto error_cb;
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return d;
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error_cb:
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bcm2835_dma_free_cb_chain(d);
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return NULL;
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}
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static int bcm2835_dma_abort(void __iomem *chan_base)
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{
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unsigned long cs;
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@ -391,12 +540,11 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
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unsigned long flags)
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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enum dma_slave_buswidth dev_width;
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struct bcm2835_desc *d;
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dma_addr_t dev_addr;
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unsigned int es, sync_type;
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unsigned int frame;
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int i;
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dma_addr_t src, dst;
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u32 info = BCM2835_DMA_WAIT_RESP;
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u32 extra = BCM2835_DMA_INT_EN;
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size_t frames;
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/* Grab configuration */
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if (!is_slave_direction(direction)) {
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@ -404,104 +552,58 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
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return NULL;
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}
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if (direction == DMA_DEV_TO_MEM) {
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dev_addr = c->cfg.src_addr;
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dev_width = c->cfg.src_addr_width;
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sync_type = BCM2835_DMA_S_DREQ;
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} else {
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dev_addr = c->cfg.dst_addr;
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dev_width = c->cfg.dst_addr_width;
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sync_type = BCM2835_DMA_D_DREQ;
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}
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/* Bus width translates to the element size (ES) */
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switch (dev_width) {
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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es = BCM2835_DMA_DATA_TYPE_S32;
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break;
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default:
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if (!buf_len) {
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dev_err(chan->device->dev,
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"%s: bad buffer length (= 0)\n", __func__);
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return NULL;
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}
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/* Now allocate and setup the descriptor. */
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d = kzalloc(sizeof(*d), GFP_NOWAIT);
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if (!d)
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return NULL;
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d->c = c;
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d->dir = direction;
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d->frames = buf_len / period_len;
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d->cyclic = true;
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d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL);
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if (!d->cb_list) {
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kfree(d);
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return NULL;
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}
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/* Allocate memory for control blocks */
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for (i = 0; i < d->frames; i++) {
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struct bcm2835_cb_entry *cb_entry = &d->cb_list[i];
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cb_entry->cb = dma_pool_zalloc(c->cb_pool, GFP_ATOMIC,
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&cb_entry->paddr);
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if (!cb_entry->cb)
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goto error_cb;
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}
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/*
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* Iterate over all frames, create a control block
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* for each frame and link them together.
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* warn if buf_len is not a multiple of period_len - this may leed
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* to unexpected latencies for interrupts and thus audiable clicks
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*/
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for (frame = 0; frame < d->frames; frame++) {
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struct bcm2835_dma_cb *control_block = d->cb_list[frame].cb;
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if (buf_len % period_len)
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dev_warn_once(chan->device->dev,
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"%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
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__func__, buf_len, period_len);
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/* Setup adresses */
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if (d->dir == DMA_DEV_TO_MEM) {
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control_block->info = BCM2835_DMA_D_INC;
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control_block->src = dev_addr;
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control_block->dst = buf_addr + frame * period_len;
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} else {
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control_block->info = BCM2835_DMA_S_INC;
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control_block->src = buf_addr + frame * period_len;
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control_block->dst = dev_addr;
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}
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/* Setup DREQ channel */
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if (c->dreq != 0)
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info |= BCM2835_DMA_PER_MAP(c->dreq);
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/* Enable interrupt */
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control_block->info |= BCM2835_DMA_INT_EN;
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/* Setup synchronization */
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if (sync_type != 0)
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control_block->info |= sync_type;
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/* Setup DREQ channel */
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if (c->dreq != 0)
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control_block->info |=
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BCM2835_DMA_PER_MAP(c->dreq);
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/* Length of a frame */
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control_block->length = period_len;
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d->size += control_block->length;
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/*
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* Next block is the next frame.
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* This DMA engine driver currently only supports cyclic DMA.
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* Therefore, wrap around at number of frames.
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*/
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control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr;
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if (direction == DMA_DEV_TO_MEM) {
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if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
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return NULL;
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src = c->cfg.src_addr;
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dst = buf_addr;
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info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
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} else {
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if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
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return NULL;
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dst = c->cfg.dst_addr;
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src = buf_addr;
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info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
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}
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/* calculate number of frames */
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frames = DIV_ROUND_UP(buf_len, period_len);
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/*
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* allocate the CB chain
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* note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
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* implementation calls prep_dma_cyclic with interrupts disabled.
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*/
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d = bcm2835_dma_create_cb_chain(chan, direction, true,
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info, extra,
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frames, src, dst, buf_len,
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period_len, GFP_NOWAIT);
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if (!d)
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return NULL;
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/* wrap around into a loop */
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d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
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return vchan_tx_prep(&c->vc, &d->vd, flags);
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error_cb:
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i--;
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for (; i >= 0; i--) {
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struct bcm2835_cb_entry *cb_entry = &d->cb_list[i];
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dma_pool_free(c->cb_pool, cb_entry->cb, cb_entry->paddr);
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}
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kfree(d->cb_list);
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kfree(d);
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return NULL;
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}
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static int bcm2835_dma_slave_config(struct dma_chan *chan,
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