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net/phy/vitesse: Configure RGMII skew on VSC8601, if needed
With RGMII, we need a 1.5 to 2ns skew between clock and data lines. The VSC8601 can handle this internally. While the VSC8601 can set more fine-grained delays, the standard skew settings work out of the box. The same heuristic is used to determine when this skew should be enabled as in vsc824x_config_init(). Tested on custom board with AM3352 SOC and VSC801 PHY. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -62,6 +62,10 @@
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/* Vitesse Extended Page Access Register */
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#define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
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/* Vitesse VSC8601 Extended PHY Control Register 1 */
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#define MII_VSC8601_EPHY_CTL 0x17
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#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
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#define PHY_ID_VSC8234 0x000fc620
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#define PHY_ID_VSC8244 0x000fc6c0
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#define PHY_ID_VSC8514 0x00070670
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@ -111,6 +115,34 @@ static int vsc824x_config_init(struct phy_device *phydev)
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return err;
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}
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/* This adds a skew for both TX and RX clocks, so the skew should only be
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* applied to "rgmii-id" interfaces. It may not work as expected
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* on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
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static int vsc8601_add_skew(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
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if (ret < 0)
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return ret;
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ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
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return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
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}
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static int vsc8601_config_init(struct phy_device *phydev)
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{
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int ret = 0;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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ret = vsc8601_add_skew(phydev);
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if (ret < 0)
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return ret;
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return genphy_config_init(phydev);
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}
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static int vsc824x_ack_interrupt(struct phy_device *phydev)
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{
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int err = 0;
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@ -275,7 +307,7 @@ static struct phy_driver vsc82xx_driver[] = {
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.phy_id_mask = 0x000ffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_init = &genphy_config_init,
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.config_init = &vsc8601_config_init,
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.config_aneg = &genphy_config_aneg,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc824x_ack_interrupt,
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