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UniPhier ARM SoC updates for v4.9
* Remove unneeded SMP code -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXxgMzAAoJED2LAQed4NsGZcYP/ii71ytpSH9JKa2gPamGBrXb tCcuURzgzDajGVMKiO2dRGMJiUlJQnZBsynUPzz37nh46838hVC73Dqklgs8Q4SG f2RHmU9BKmvTLpm23iVArbaT+UqYT5vsSa1oz1XRfeU4QnqSf3JS/zaCFj/mStrR VnHBFykXgi1CyIDgqcjCKSSV4z2ZUTUVB/vZlFIMJk/HagnD2GoreZN7eJxwY7hW B7UGpnkUYGtQv+jVJVd9VJOOL9va3kHiDLzTaflBkKne0GBN5NwxYPuxgBc8sJ4a SDIa7dBlNbILpa0kcZq71UjsMvssExHThZYKZzkmtEUb0p4zns+50Pt0Ejz7xxDI ud9bZ7nOurBUUzfLNX2CAKwvPKrs1pVPRF1+zTQfNh2wrXDjmoMMvZNwBsBZNB1v eHzDZODqtdqmncXPM6Ixf2vVFskb+mjIoMASiVnoG6R2MdoOPi9l25qtUhSLkiok NWkLWrsxM9vr2ghedDjHDG7mhIK0c0arJb51Z5Av1w3zFttY3037qvzORGmZ6/35 qvJMJZ5QRLwP9Esbb81imGGemvmsOPf0oOzINfrALeAOggLjsUP2uHEpk/9a9Wxx hEpWjhd02I7/+vY0iNyHa1RV6htlJzMS/1atpY4qORGRxnppgB4li/INSG7yILkt nveINr4i8xXNCZXQ51ig =IZcN -----END PGP SIGNATURE----- Merge tag 'uniphier-soc-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/soc Pull "UniPhier ARM SoC updates for v4.9" from Masahiro Yamada: * Remove unneeded SMP code * tag 'uniphier-soc-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: ARM: uniphier: remove SoC-specific SMP code
This commit is contained in:
Arnd Bergmann
commit
95ab29a1f1
@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -19,28 +20,11 @@
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#ifdef CONFIG_CACHE_UNIPHIER
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int uniphier_cache_init(void);
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int uniphier_cache_l2_is_enabled(void);
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void uniphier_cache_l2_touch_range(unsigned long start, unsigned long end);
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void uniphier_cache_l2_set_locked_ways(u32 way_mask);
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#else
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static inline int uniphier_cache_init(void)
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{
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return -ENODEV;
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}
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static inline int uniphier_cache_l2_is_enabled(void)
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{
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return 0;
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}
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static inline void uniphier_cache_l2_touch_range(unsigned long start,
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unsigned long end)
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{
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}
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static inline void uniphier_cache_l2_set_locked_ways(u32 way_mask)
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{
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}
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#endif
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#endif /* __CACHE_UNIPHIER_H */
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@ -1 +1 @@
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj- += dummy.o
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@ -1,43 +0,0 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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ENTRY(uniphier_smp_trampoline)
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ARM_BE8(setend be) @ ensure we are in BE8 mode
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
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and r2, r0, #0x3 @ CPU ID
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ldr r1, uniphier_smp_trampoline_jump
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ldr r3, uniphier_smp_trampoline_poll_addr
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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orr r0, r0, #CR_I @ Enable ICache
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bic r0, r0, #(CR_C | CR_M) @ Disable MMU and Dcache
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mcr p15, 0, r0, c1, c0, 0
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b 1f @ cache the following 5 instructions
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0: wfe
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1: ldr r0, [r3]
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cmp r0, r2
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bxeq r1 @ branch to secondary_startup
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b 0b
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.globl uniphier_smp_trampoline_jump
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uniphier_smp_trampoline_jump:
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.word 0 @ set virt_to_phys(secondary_startup)
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.globl uniphier_smp_trampoline_poll_addr
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uniphier_smp_trampoline_poll_addr:
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.word 0 @ set CPU ID to be kicked to this reg
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.globl uniphier_smp_trampoline_end
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uniphier_smp_trampoline_end:
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ENDPROC(uniphier_smp_trampoline)
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@ -1,209 +0,0 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "uniphier: " fmt
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/sizes.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-uniphier.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/smp_scu.h>
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/*
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* The secondary CPUs check this register from the boot ROM for the jump
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* destination. After that, it can be reused as a scratch register.
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*/
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#define UNIPHIER_SMPCTRL_ROM_RSV2 0x208
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static void __iomem *uniphier_smp_rom_boot_rsv2;
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static unsigned int uniphier_smp_max_cpus;
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extern char uniphier_smp_trampoline;
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extern char uniphier_smp_trampoline_jump;
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extern char uniphier_smp_trampoline_poll_addr;
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extern char uniphier_smp_trampoline_end;
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/*
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* Copy trampoline code to the tail of the 1st section of the page table used
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* in the boot ROM. This area is directly accessible by the secondary CPUs
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* for all the UniPhier SoCs.
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*/
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static const phys_addr_t uniphier_smp_trampoline_dest_end = SECTION_SIZE;
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static phys_addr_t uniphier_smp_trampoline_dest;
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static int __init uniphier_smp_copy_trampoline(phys_addr_t poll_addr)
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{
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size_t trmp_size;
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static void __iomem *trmp_base;
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if (!uniphier_cache_l2_is_enabled()) {
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pr_warn("outer cache is needed for SMP, but not enabled\n");
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return -ENODEV;
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}
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uniphier_cache_l2_set_locked_ways(1);
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outer_flush_all();
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trmp_size = &uniphier_smp_trampoline_end - &uniphier_smp_trampoline;
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uniphier_smp_trampoline_dest = uniphier_smp_trampoline_dest_end -
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trmp_size;
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uniphier_cache_l2_touch_range(uniphier_smp_trampoline_dest,
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uniphier_smp_trampoline_dest_end);
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trmp_base = ioremap_cache(uniphier_smp_trampoline_dest, trmp_size);
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if (!trmp_base) {
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pr_err("failed to map trampoline destination area\n");
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return -ENOMEM;
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}
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memcpy(trmp_base, &uniphier_smp_trampoline, trmp_size);
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writel(virt_to_phys(secondary_startup),
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trmp_base + (&uniphier_smp_trampoline_jump -
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&uniphier_smp_trampoline));
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writel(poll_addr, trmp_base + (&uniphier_smp_trampoline_poll_addr -
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&uniphier_smp_trampoline));
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flush_cache_all(); /* flush out trampoline code to outer cache */
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iounmap(trmp_base);
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return 0;
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}
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static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus)
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{
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struct device_node *np;
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struct resource res;
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phys_addr_t rom_rsv2_phys;
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int ret;
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np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-smpctrl");
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ret = of_address_to_resource(np, 0, &res);
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of_node_put(np);
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if (ret) {
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pr_err("failed to get resource of SMP control\n");
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return ret;
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}
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rom_rsv2_phys = res.start + UNIPHIER_SMPCTRL_ROM_RSV2;
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ret = uniphier_smp_copy_trampoline(rom_rsv2_phys);
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if (ret)
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return ret;
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uniphier_smp_rom_boot_rsv2 = ioremap(rom_rsv2_phys, SZ_4);
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if (!uniphier_smp_rom_boot_rsv2) {
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pr_err("failed to map ROM_BOOT_RSV2 register\n");
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return -ENOMEM;
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}
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writel(uniphier_smp_trampoline_dest, uniphier_smp_rom_boot_rsv2);
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asm("sev"); /* Bring up all secondary CPUs to the trampoline code */
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uniphier_smp_max_cpus = max_cpus; /* save for later use */
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return 0;
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}
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static void __init uniphier_smp_unprepare_trampoline(void)
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{
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iounmap(uniphier_smp_rom_boot_rsv2);
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if (uniphier_smp_trampoline_dest)
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outer_inv_range(uniphier_smp_trampoline_dest,
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uniphier_smp_trampoline_dest_end);
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uniphier_cache_l2_set_locked_ways(0);
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}
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static int __init uniphier_smp_enable_scu(void)
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{
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unsigned long scu_base_phys = 0;
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void __iomem *scu_base;
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if (scu_a9_has_base())
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scu_base_phys = scu_a9_get_base();
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if (!scu_base_phys) {
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pr_err("failed to get scu base\n");
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return -ENODEV;
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}
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scu_base = ioremap(scu_base_phys, SZ_128);
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if (!scu_base) {
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pr_err("failed to map scu base\n");
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return -ENOMEM;
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}
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scu_enable(scu_base);
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iounmap(scu_base);
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return 0;
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}
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static void __init uniphier_smp_prepare_cpus(unsigned int max_cpus)
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{
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static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
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int ret;
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ret = uniphier_smp_prepare_trampoline(max_cpus);
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if (ret)
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goto err;
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ret = uniphier_smp_enable_scu();
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if (ret)
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goto err;
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return;
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err:
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pr_warn("disabling SMP\n");
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init_cpu_present(&only_cpu_0);
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uniphier_smp_unprepare_trampoline();
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}
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static int __init uniphier_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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if (WARN_ON_ONCE(!uniphier_smp_rom_boot_rsv2))
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return -EFAULT;
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writel(cpu, uniphier_smp_rom_boot_rsv2);
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readl(uniphier_smp_rom_boot_rsv2); /* relax */
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asm("sev"); /* wake up secondary CPUs sleeping in the trampoline */
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if (cpu == uniphier_smp_max_cpus - 1) {
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/* clean up resources if this is the last CPU */
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uniphier_smp_unprepare_trampoline();
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}
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return 0;
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}
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static const struct smp_operations uniphier_smp_ops __initconst = {
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.smp_prepare_cpus = uniphier_smp_prepare_cpus,
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.smp_boot_secondary = uniphier_smp_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(uniphier_smp, "socionext,uniphier-smp",
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&uniphier_smp_ops);
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -43,27 +44,15 @@
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#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
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#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
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#define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
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#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
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#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
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#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
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#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
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#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
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#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
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#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
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#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
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#define UNIPHIER_SSCOQM_CE BIT(15) /* notify completion */
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#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
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#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
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#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
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#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
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#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
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#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
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#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
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#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
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#define UNIPHIER_SSCOQAD 0x24c /* Cache Operation Queue Address */
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#define UNIPHIER_SSCOQSZ 0x250 /* Cache Operation Queue Size */
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#define UNIPHIER_SSCOQMASK 0x254 /* Cache Operation Queue Address Mask */
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#define UNIPHIER_SSCOQWN 0x258 /* Cache Operation Queue Way Number */
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#define UNIPHIER_SSCOPPQSEF 0x25c /* Cache Operation Queue Set Complete*/
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#define UNIPHIER_SSCOPPQSEF_FE BIT(1)
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#define UNIPHIER_SSCOPPQSEF_OE BIT(0)
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@ -72,9 +61,6 @@
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#define UNIPHIER_SSCOLPQS_EST BIT(1)
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#define UNIPHIER_SSCOLPQS_QST BIT(0)
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/* Is the touch/pre-fetch destination specified by ways? */
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#define UNIPHIER_SSCOQM_TID_IS_WAY(op) \
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((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)
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/* Is the operation region specified by address range? */
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#define UNIPHIER_SSCOQM_S_IS_RANGE(op) \
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((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
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@ -178,11 +164,6 @@ static void __uniphier_cache_maint_common(struct uniphier_cache_data *data,
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writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD);
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writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ);
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}
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/* set target ways if needed */
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if (unlikely(UNIPHIER_SSCOQM_TID_IS_WAY(operation)))
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writel_relaxed(data->way_locked_mask,
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data->op_base + UNIPHIER_SSCOQWN);
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} while (unlikely(readl_relaxed(data->op_base + UNIPHIER_SSCOPPQSEF) &
|
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(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
|
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|
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@ -338,46 +319,8 @@ static void uniphier_cache_sync(void)
|
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__uniphier_cache_sync(data);
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}
|
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|
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int __init uniphier_cache_l2_is_enabled(void)
|
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{
|
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struct uniphier_cache_data *data;
|
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|
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data = list_first_entry_or_null(&uniphier_cache_list,
|
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struct uniphier_cache_data, list);
|
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if (!data)
|
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return 0;
|
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|
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return !!(readl_relaxed(data->ctrl_base + UNIPHIER_SSCC) &
|
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UNIPHIER_SSCC_ON);
|
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}
|
||||
|
||||
void __init uniphier_cache_l2_touch_range(unsigned long start,
|
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unsigned long end)
|
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{
|
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struct uniphier_cache_data *data;
|
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|
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data = list_first_entry_or_null(&uniphier_cache_list,
|
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struct uniphier_cache_data, list);
|
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if (data)
|
||||
__uniphier_cache_maint_range(data, start, end,
|
||||
UNIPHIER_SSCOQM_TID_WAY |
|
||||
UNIPHIER_SSCOQM_CM_TOUCH);
|
||||
}
|
||||
|
||||
void __init uniphier_cache_l2_set_locked_ways(u32 way_mask)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
data = list_first_entry_or_null(&uniphier_cache_list,
|
||||
struct uniphier_cache_data, list);
|
||||
if (data)
|
||||
__uniphier_cache_set_locked_ways(data, way_mask);
|
||||
}
|
||||
|
||||
static const struct of_device_id uniphier_cache_match[] __initconst = {
|
||||
{
|
||||
.compatible = "socionext,uniphier-system-cache",
|
||||
},
|
||||
{ .compatible = "socionext,uniphier-system-cache" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user