FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2024-12-15 13:22:55 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Renesas ARM based SoC fixes for v3.13

Browse Source 
* r8a7790 (R-Car H1) SoC
   - Correct GPIO resources in DT.
 
     This problem has been present since GPIOs were added to the r8a7790 SoC
     by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
     devices to device tree") in v3.12-rc1.
 
 * irqchip renesas-intc-irqpin
   - Correct register bitfield shift calculation
 
     This bug has been present since the renesas-intc-irqpin driver was
     introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
     driver") in v3.10-rc1
 
 * Lager board
   - Do not build the phy fixup unless CONFIG_PHYLIB is enabled
 
     This problem was introduced by 48c8b96f21
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.15 (GNU/Linux)
 
 iQIcBAABAgAGBQJSqmcQAAoJENfPZGlqN0++VTgP/3II1c6Wge1s9TjQ2FnD874X
 wVMLAY8oJp+mNiiov+iNtnP0deyjgWr2XfwQ8QNsWTVEAPQjvInOydr7B24SFb7e
 FnA5gscGQr49xMorR+x8yUnlyIE6UAbwwgbP2GljsrTZFURo9ohfUA3LP9wSPHJ9
 MYRopGb7ZlNaTwxEi5t6rZV3mrBSzbSUZ0YbQbN5vAhm1zoZ7hzfXUsk9ZwhVNnI
 RFHOy01DDCb0EM8Yut4DfWMri9VgsMcR+bo73Js1ljpkUujCzJsr5fNlpzCi2unX
 Xw9s6WCSNaNGLzgGbbLojAUIkrtMUEp/XT2iATIalKHT0zULqe6kNcnonFJ8GmQk
 nrNBF4/rn45S4QFSEiqavrWpmVE78pMEzPTBpmR15+KloLuutdYrqb/HUM60lVh3
 zVeL2cG9fTFx2CUODNX9ABGlO7CCDz4MgK5RgSpnnxjIgunLEb4gA+6ncqaQ4XhM
 Ldicte6ppq26PNQemiL61PbfVVNE6hcW//IZreFUEQkP2Ls/DzWfBVtOQaWj3fpb
 DEK/kvHGA1HVrLTt43WVM5kPy5OMKDGFv6w7NRayTMvUDguuwp5QeGxSFsi/104Z
 q5Qaekvi0wIGaWfkRGHB/8o9z/zL/ifW/cqNXqW1Yxf2+KZGuRWIpxZLzMwBfhzb
 LoENHwKcU/D7YhzXIGHG
 =Vbzt
 -----END PGP SIGNATURE-----

Merge tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes

From Simon Horman:
Renesas ARM based SoC fixes for v3.13

* r8a7790 (R-Car H1) SoC
  - Correct GPIO resources in DT.

    This problem has been present since GPIOs were added to the r8a7790 SoC
    by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
    devices to device tree") in v3.12-rc1.

* irqchip renesas-intc-irqpin
  - Correct register bitfield shift calculation

    This bug has been present since the renesas-intc-irqpin driver was
    introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
    driver") in v3.10-rc1

* Lager board
  - Do not build the phy fixup unless CONFIG_PHYLIB is enabled

    This problem was introduced by 48c8b96f21

* tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7790: Fix GPIO resources in DTS
  irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
  ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB

Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman 2013-12-20 11:27:12 -08:00
commit 95fcfa70f3
3 changed files with 20 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -87,9 +87,9 @@
interrupts = <1 9 0xf04>;
};
gpio0: gpio@ffc40000 {
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
reg = <0 0xffc40000 0 0x2c>;
reg = <0 0xe6050000 0 0x50>;
interrupt-parent = <&gic>;
interrupts = <0 4 0x4>;
#gpio-cells = <2>;
@ -99,9 +99,9 @@
interrupt-controller;
};
gpio1: gpio@ffc41000 {
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
reg = <0 0xffc41000 0 0x2c>;
reg = <0 0xe6051000 0 0x50>;
interrupt-parent = <&gic>;
interrupts = <0 5 0x4>;
#gpio-cells = <2>;
@ -111,9 +111,9 @@
interrupt-controller;
};
gpio2: gpio@ffc42000 {
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
reg = <0 0xffc42000 0 0x2c>;
reg = <0 0xe6052000 0 0x50>;
interrupt-parent = <&gic>;
interrupts = <0 6 0x4>;
#gpio-cells = <2>;
@ -123,9 +123,9 @@
interrupt-controller;
};
gpio3: gpio@ffc43000 {
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
reg = <0 0xffc43000 0 0x2c>;
reg = <0 0xe6053000 0 0x50>;
interrupt-parent = <&gic>;
interrupts = <0 7 0x4>;
#gpio-cells = <2>;
@ -135,9 +135,9 @@
interrupt-controller;
};
gpio4: gpio@ffc44000 {
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
reg = <0 0xffc44000 0 0x2c>;
reg = <0 0xe6054000 0 0x50>;
interrupt-parent = <&gic>;
interrupts = <0 8 0x4>;
#gpio-cells = <2>;
@ -147,9 +147,9 @@
interrupt-controller;
};
gpio5: gpio@ffc45000 {
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
reg = <0 0xffc45000 0 0x2c>;
reg = <0 0xe6055000 0 0x50>;
interrupt-parent = <&gic>;
interrupts = <0 9 0x4>;
#gpio-cells = <2>;

4
arch/arm/mach-shmobile/board-lager.c
View File

@ -245,7 +245,9 @@ static void __init lager_init(void)
{
lager_add_standard_devices();
phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
if (IS_ENABLED(CONFIG_PHYLIB))
phy_register_fixup_for_id("r8a7790-ether-ff:01",
lager_ksz8041_fixup);
}
static const char * const lager_boards_compat_dt[] __initconst = {

8
drivers/irqchip/irq-renesas-intc-irqpin.c
View File

@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
int irq, int do_mask)
{
int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
int bitfield_width = 4;
int shift = 32 - (irq + 1) * bitfield_width;
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
shift, bitfield_width,
@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
{
/* The SENSE register is assumed to be 32-bit. */
int bitfield_width = p->config.sense_bitfield_width;
int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
int shift = 32 - (irq + 1) * bitfield_width;
dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);