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ARM: tegra: clock: Add function to set SDMMC tap delay

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The SDMMC controllers have extra bits in the clock source
register that adjust the delay between the clock and data
to compenstate for delays on the PCB.  The values need to
be set from the clock code so the clock can be locked
during the read-modify-write on the clock source register.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
Colin Cross 2011-02-12 18:24:32 -08:00
parent 7a28128412
commit 9743b38969
4 changed files with 36 additions and 0 deletions
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14
arch/arm/mach-tegra/clock.c
View File

@ -390,6 +390,20 @@ void __init tegra_init_clock(void)
tegra2_init_clocks();
}
/*
* The SDMMC controllers have extra bits in the clock source register that
* adjust the delay between the clock and data to compenstate for delays
* on the PCB.
*/
void tegra_sdmmc_tap_delay(struct clk *c, int delay)
{
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
tegra2_sdmmc_tap_delay(c, delay);
spin_unlock_irqrestore(&c->spinlock, flags);
}
#ifdef CONFIG_DEBUG_FS
static int __clk_lock_all_spinlocks(void)

1
arch/arm/mach-tegra/clock.h
View File

@ -155,5 +155,6 @@ int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
unsigned long clk_get_rate_locked(struct clk *c);
int clk_set_rate_locked(struct clk *c, unsigned long rate);
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif

2
arch/arm/mach-tegra/include/mach/clk.h
View File

@ -26,4 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
unsigned long clk_get_rate_all_locked(struct clk *c);
void tegra_sdmmc_tap_delay(struct clk *c, int delay);
#endif

19
arch/arm/mach-tegra/tegra2_clocks.c
View File

@ -74,6 +74,10 @@
#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
#define SDMMC_CLK_INT_FB_SEL (1 << 23)
#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
#define PLL_BASE 0x0
#define PLL_BASE_BYPASS (1<<31)
#define PLL_BASE_ENABLE (1<<30)
@ -1052,6 +1056,21 @@ static struct clk_ops tegra_periph_clk_ops = {
.reset = &tegra2_periph_clk_reset,
};
/* The SDMMC controllers have extra bits in the clock source register that
* adjust the delay between the clock and data to compenstate for delays
* on the PCB. */
void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
{
u32 reg;
delay = clamp(delay, 0, 15);
reg = clk_readl(c->reg);
reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
reg |= SDMMC_CLK_INT_FB_SEL;
reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
clk_writel(reg, c->reg);
}
/* External memory controller clock ops */
static void tegra2_emc_clk_init(struct clk *c)
{