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Merge tag 'drm-intel-fixes-2016-09-15' of git://anongit.freedesktop.org/drm-intel into drm-fixes
i915 fixes from Jani. * tag 'drm-intel-fixes-2016-09-15' of git://anongit.freedesktop.org/drm-intel: drm/i915: Ignore OpRegion panel type except on select machines Revert "drm/i915/psr: Make idle_frames sensible again" drm/i915: Restore lost "Initialized i915" welcome message
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commit
9929c09767
@ -1281,6 +1281,11 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
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intel_runtime_pm_enable(dev_priv);
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/* Everything is in place, we can now relax! */
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DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
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driver.name, driver.major, driver.minor, driver.patchlevel,
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driver.date, pci_name(pdev), dev_priv->drm.primary->index);
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intel_runtime_pm_put(dev_priv);
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return 0;
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@ -1047,6 +1047,23 @@ err_out:
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return err;
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}
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static int intel_use_opregion_panel_type_callback(const struct dmi_system_id *id)
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{
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DRM_INFO("Using panel type from OpRegion on %s\n", id->ident);
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return 1;
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}
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static const struct dmi_system_id intel_use_opregion_panel_type[] = {
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{
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.callback = intel_use_opregion_panel_type_callback,
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.ident = "Conrac GmbH IX45GM2",
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.matches = {DMI_MATCH(DMI_SYS_VENDOR, "Conrac GmbH"),
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DMI_MATCH(DMI_PRODUCT_NAME, "IX45GM2"),
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},
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},
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{ }
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};
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int
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intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
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{
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@ -1072,6 +1089,16 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
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return -ENODEV;
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}
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/*
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* So far we know that some machined must use it, others must not use it.
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* There doesn't seem to be any way to determine which way to go, except
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* via a quirk list :(
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*/
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if (!dmi_check_system(intel_use_opregion_panel_type)) {
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DRM_DEBUG_KMS("Ignoring OpRegion panel type (%d)\n", ret - 1);
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return -ENODEV;
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}
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/*
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* FIXME On Dell XPS 13 9350 the OpRegion panel type (0) gives us
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* low vswing for eDP, whereas the VBT panel type (2) gives us normal
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@ -255,14 +255,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = to_i915(dev);
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uint32_t max_sleep_time = 0x1f;
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/* Lately it was identified that depending on panel idle frame count
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* calculated at HW can be off by 1. So let's use what came
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* from VBT + 1.
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* There are also other cases where panel demands at least 4
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* but VBT is not being set. To cover these 2 cases lets use
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* at least 5 when VBT isn't set to be on the safest side.
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/*
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* Let's respect VBT in case VBT asks a higher idle_frame value.
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* Let's use 6 as the minimum to cover all known cases including
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* the off-by-one issue that HW has in some cases. Also there are
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* cases where sink should be able to train
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* with the 5 or 6 idle patterns.
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*/
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uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1;
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uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
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uint32_t val = EDP_PSR_ENABLE;
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val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
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