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Merge branches 'pm-cpuidle', 'pm-cpufreq' and 'pm-sleep'

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* pm-cpuidle:
  intel_idle: stop exposing platform acronyms in sysfs
  cpuidle: menu: Avoid taking spinlock for accessing QoS values

* pm-cpufreq:
  cpufreq: intel_pstate: Fix limits issue with operation mode switching
  cpufreq: qoriq: clean up unused code

* pm-sleep:
  PM / hibernate: Define pr_fmt() and use pr_*() instead of printk()
  PM / hibernate: Untangle power_down()
This commit is contained in:
Rafael J. Wysocki 2017-03-03 00:43:11 +01:00
commit 9b5e9cb164
7 changed files with 161 additions and 185 deletions
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3
drivers/base/power/qos.c
View File

@ -103,8 +103,7 @@ s32 __dev_pm_qos_read_value(struct device *dev)
{
lockdep_assert_held(&dev->power.lock);
return IS_ERR_OR_NULL(dev->power.qos) ?
0 : pm_qos_read_value(&dev->power.qos->resume_latency);
return dev_pm_qos_raw_read_value(dev);
}
/**

65
drivers/cpufreq/intel_pstate.c
View File

@ -364,37 +364,25 @@ static bool driver_registered __read_mostly;
static bool acpi_ppc;
#endif
static struct perf_limits performance_limits = {
.no_turbo = 0,
.turbo_disabled = 0,
.max_perf_pct = 100,
.max_perf = int_ext_tofp(1),
.min_perf_pct = 100,
.min_perf = int_ext_tofp(1),
.max_policy_pct = 100,
.max_sysfs_pct = 100,
.min_policy_pct = 0,
.min_sysfs_pct = 0,
};
static struct perf_limits performance_limits;
static struct perf_limits powersave_limits;
static struct perf_limits *limits;
static struct perf_limits powersave_limits = {
.no_turbo = 0,
.turbo_disabled = 0,
.max_perf_pct = 100,
.max_perf = int_ext_tofp(1),
.min_perf_pct = 0,
.min_perf = 0,
.max_policy_pct = 100,
.max_sysfs_pct = 100,
.min_policy_pct = 0,
.min_sysfs_pct = 0,
};
static void intel_pstate_init_limits(struct perf_limits *limits)
{
memset(limits, 0, sizeof(*limits));
limits->max_perf_pct = 100;
limits->max_perf = int_ext_tofp(1);
limits->max_policy_pct = 100;
limits->max_sysfs_pct = 100;
}
#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
static struct perf_limits *limits = &performance_limits;
#else
static struct perf_limits *limits = &powersave_limits;
#endif
static void intel_pstate_set_performance_limits(struct perf_limits *limits)
{
intel_pstate_init_limits(limits);
limits->min_perf_pct = 100;
limits->min_perf = int_ext_tofp(1);
}
static DEFINE_MUTEX(intel_pstate_driver_lock);
static DEFINE_MUTEX(intel_pstate_limits_lock);
@ -2084,20 +2072,6 @@ static void intel_pstate_clear_update_util_hook(unsigned int cpu)
synchronize_sched();
}
static void intel_pstate_set_performance_limits(struct perf_limits *limits)
{
limits->no_turbo = 0;
limits->turbo_disabled = 0;
limits->max_perf_pct = 100;
limits->max_perf = int_ext_tofp(1);
limits->min_perf_pct = 100;
limits->min_perf = int_ext_tofp(1);
limits->max_policy_pct = 100;
limits->max_sysfs_pct = 100;
limits->min_policy_pct = 0;
limits->min_sysfs_pct = 0;
}
static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
struct perf_limits *limits)
{
@ -2466,6 +2440,11 @@ static int intel_pstate_register_driver(void)
{
int ret;
intel_pstate_init_limits(&powersave_limits);
intel_pstate_set_performance_limits(&performance_limits);
limits = IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) ?
&performance_limits : &powersave_limits;
ret = cpufreq_register_driver(intel_pstate_driver);
if (ret) {
intel_pstate_driver_cleanup();

4
drivers/cpufreq/qoriq-cpufreq.c
View File

@ -23,10 +23,6 @@
#include <linux/slab.h>
#include <linux/smp.h>
#if !defined(CONFIG_ARM)
#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
#endif
/**
* struct cpu_data
* @pclk: the parent clock of cpu

2
drivers/cpuidle/governors/menu.c
View File

@ -287,7 +287,7 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev)
unsigned int interactivity_req;
unsigned int expected_interval;
unsigned long nr_iowaiters, cpu_load;
int resume_latency = dev_pm_qos_read_value(device);
int resume_latency = dev_pm_qos_raw_read_value(device);
if (data->needs_update) {
menu_update(drv, dev);

172
drivers/idle/intel_idle.c
View File

@ -125,7 +125,7 @@ static struct cpuidle_state *cpuidle_state_table;
*/
static struct cpuidle_state nehalem_cstates[] = {
{
.name = "C1-NHM",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 3,
@ -133,7 +133,7 @@ static struct cpuidle_state nehalem_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-NHM",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -141,7 +141,7 @@ static struct cpuidle_state nehalem_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-NHM",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 20,
@ -149,7 +149,7 @@ static struct cpuidle_state nehalem_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-NHM",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 200,
@ -162,7 +162,7 @@ static struct cpuidle_state nehalem_cstates[] = {
static struct cpuidle_state snb_cstates[] = {
{
.name = "C1-SNB",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -170,7 +170,7 @@ static struct cpuidle_state snb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-SNB",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -178,7 +178,7 @@ static struct cpuidle_state snb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-SNB",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 80,
@ -186,7 +186,7 @@ static struct cpuidle_state snb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-SNB",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 104,
@ -194,7 +194,7 @@ static struct cpuidle_state snb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7-SNB",
.name = "C7",
.desc = "MWAIT 0x30",
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 109,
@ -207,7 +207,7 @@ static struct cpuidle_state snb_cstates[] = {
static struct cpuidle_state byt_cstates[] = {
{
.name = "C1-BYT",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -215,7 +215,7 @@ static struct cpuidle_state byt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6N-BYT",
.name = "C6N",
.desc = "MWAIT 0x58",
.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 300,
@ -223,7 +223,7 @@ static struct cpuidle_state byt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6S-BYT",
.name = "C6S",
.desc = "MWAIT 0x52",
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 500,
@ -231,7 +231,7 @@ static struct cpuidle_state byt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7-BYT",
.name = "C7",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 1200,
@ -239,7 +239,7 @@ static struct cpuidle_state byt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7S-BYT",
.name = "C7S",
.desc = "MWAIT 0x64",
.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 10000,
@ -252,7 +252,7 @@ static struct cpuidle_state byt_cstates[] = {
static struct cpuidle_state cht_cstates[] = {
{
.name = "C1-CHT",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -260,7 +260,7 @@ static struct cpuidle_state cht_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6N-CHT",
.name = "C6N",
.desc = "MWAIT 0x58",
.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 80,
@ -268,7 +268,7 @@ static struct cpuidle_state cht_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6S-CHT",
.name = "C6S",
.desc = "MWAIT 0x52",
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 200,
@ -276,7 +276,7 @@ static struct cpuidle_state cht_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7-CHT",
.name = "C7",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 1200,
@ -284,7 +284,7 @@ static struct cpuidle_state cht_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7S-CHT",
.name = "C7S",
.desc = "MWAIT 0x64",
.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 10000,
@ -297,7 +297,7 @@ static struct cpuidle_state cht_cstates[] = {
static struct cpuidle_state ivb_cstates[] = {
{
.name = "C1-IVB",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -305,7 +305,7 @@ static struct cpuidle_state ivb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-IVB",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -313,7 +313,7 @@ static struct cpuidle_state ivb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-IVB",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 59,
@ -321,7 +321,7 @@ static struct cpuidle_state ivb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-IVB",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 80,
@ -329,7 +329,7 @@ static struct cpuidle_state ivb_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7-IVB",
.name = "C7",
.desc = "MWAIT 0x30",
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 87,
@ -342,7 +342,7 @@ static struct cpuidle_state ivb_cstates[] = {
static struct cpuidle_state ivt_cstates[] = {
{
.name = "C1-IVT",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -350,7 +350,7 @@ static struct cpuidle_state ivt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-IVT",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -358,7 +358,7 @@ static struct cpuidle_state ivt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-IVT",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 59,
@ -366,7 +366,7 @@ static struct cpuidle_state ivt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-IVT",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 82,
@ -379,7 +379,7 @@ static struct cpuidle_state ivt_cstates[] = {
static struct cpuidle_state ivt_cstates_4s[] = {
{
.name = "C1-IVT-4S",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -387,7 +387,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-IVT-4S",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -395,7 +395,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-IVT-4S",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 59,
@ -403,7 +403,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-IVT-4S",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 84,
@ -416,7 +416,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
static struct cpuidle_state ivt_cstates_8s[] = {
{
.name = "C1-IVT-8S",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -424,7 +424,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-IVT-8S",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -432,7 +432,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-IVT-8S",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 59,
@ -440,7 +440,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-IVT-8S",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 88,
@ -453,7 +453,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
static struct cpuidle_state hsw_cstates[] = {
{
.name = "C1-HSW",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -461,7 +461,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-HSW",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -469,7 +469,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-HSW",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 33,
@ -477,7 +477,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-HSW",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 133,
@ -485,7 +485,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7s-HSW",
.name = "C7s",
.desc = "MWAIT 0x32",
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 166,
@ -493,7 +493,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C8-HSW",
.name = "C8",
.desc = "MWAIT 0x40",
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 300,
@ -501,7 +501,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C9-HSW",
.name = "C9",
.desc = "MWAIT 0x50",
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 600,
@ -509,7 +509,7 @@ static struct cpuidle_state hsw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C10-HSW",
.name = "C10",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 2600,
@ -521,7 +521,7 @@ static struct cpuidle_state hsw_cstates[] = {
};
static struct cpuidle_state bdw_cstates[] = {
{
.name = "C1-BDW",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -529,7 +529,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-BDW",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -537,7 +537,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-BDW",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 40,
@ -545,7 +545,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-BDW",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 133,
@ -553,7 +553,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7s-BDW",
.name = "C7s",
.desc = "MWAIT 0x32",
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 166,
@ -561,7 +561,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C8-BDW",
.name = "C8",
.desc = "MWAIT 0x40",
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 300,
@ -569,7 +569,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C9-BDW",
.name = "C9",
.desc = "MWAIT 0x50",
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 600,
@ -577,7 +577,7 @@ static struct cpuidle_state bdw_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C10-BDW",
.name = "C10",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 2600,
@ -590,7 +590,7 @@ static struct cpuidle_state bdw_cstates[] = {
static struct cpuidle_state skl_cstates[] = {
{
.name = "C1-SKL",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -598,7 +598,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-SKL",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -606,7 +606,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C3-SKL",
.name = "C3",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 70,
@ -614,7 +614,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-SKL",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 85,
@ -622,7 +622,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7s-SKL",
.name = "C7s",
.desc = "MWAIT 0x33",
.flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 124,
@ -630,7 +630,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C8-SKL",
.name = "C8",
.desc = "MWAIT 0x40",
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 200,
@ -638,7 +638,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C9-SKL",
.name = "C9",
.desc = "MWAIT 0x50",
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 480,
@ -646,7 +646,7 @@ static struct cpuidle_state skl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C10-SKL",
.name = "C10",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 890,
@ -659,7 +659,7 @@ static struct cpuidle_state skl_cstates[] = {
static struct cpuidle_state skx_cstates[] = {
{
.name = "C1-SKX",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -667,7 +667,7 @@ static struct cpuidle_state skx_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-SKX",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -675,7 +675,7 @@ static struct cpuidle_state skx_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-SKX",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 133,
@ -688,7 +688,7 @@ static struct cpuidle_state skx_cstates[] = {
static struct cpuidle_state atom_cstates[] = {
{
.name = "C1E-ATM",
.name = "C1E",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 10,
@ -696,7 +696,7 @@ static struct cpuidle_state atom_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C2-ATM",
.name = "C2",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10),
.exit_latency = 20,
@ -704,7 +704,7 @@ static struct cpuidle_state atom_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C4-ATM",
.name = "C4",
.desc = "MWAIT 0x30",
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 100,
@ -712,7 +712,7 @@ static struct cpuidle_state atom_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-ATM",
.name = "C6",
.desc = "MWAIT 0x52",
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 140,
@ -724,7 +724,7 @@ static struct cpuidle_state atom_cstates[] = {
};
static struct cpuidle_state tangier_cstates[] = {
{
.name = "C1-TNG",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -732,7 +732,7 @@ static struct cpuidle_state tangier_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C4-TNG",
.name = "C4",
.desc = "MWAIT 0x30",
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 100,
@ -740,7 +740,7 @@ static struct cpuidle_state tangier_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-TNG",
.name = "C6",
.desc = "MWAIT 0x52",
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 140,
@ -748,7 +748,7 @@ static struct cpuidle_state tangier_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7-TNG",
.name = "C7",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 1200,
@ -756,7 +756,7 @@ static struct cpuidle_state tangier_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C9-TNG",
.name = "C9",
.desc = "MWAIT 0x64",
.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 10000,
@ -768,7 +768,7 @@ static struct cpuidle_state tangier_cstates[] = {
};
static struct cpuidle_state avn_cstates[] = {
{
.name = "C1-AVN",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -776,7 +776,7 @@ static struct cpuidle_state avn_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-AVN",
.name = "C6",
.desc = "MWAIT 0x51",
.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 15,
@ -788,7 +788,7 @@ static struct cpuidle_state avn_cstates[] = {
};
static struct cpuidle_state knl_cstates[] = {
{
.name = "C1-KNL",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 1,
@ -796,7 +796,7 @@ static struct cpuidle_state knl_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze },
{
.name = "C6-KNL",
.name = "C6",
.desc = "MWAIT 0x10",
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 120,
@ -809,7 +809,7 @@ static struct cpuidle_state knl_cstates[] = {
static struct cpuidle_state bxt_cstates[] = {
{
.name = "C1-BXT",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -817,7 +817,7 @@ static struct cpuidle_state bxt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-BXT",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -825,7 +825,7 @@ static struct cpuidle_state bxt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-BXT",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 133,
@ -833,7 +833,7 @@ static struct cpuidle_state bxt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C7s-BXT",
.name = "C7s",
.desc = "MWAIT 0x31",
.flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 155,
@ -841,7 +841,7 @@ static struct cpuidle_state bxt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C8-BXT",
.name = "C8",
.desc = "MWAIT 0x40",
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 1000,
@ -849,7 +849,7 @@ static struct cpuidle_state bxt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C9-BXT",
.name = "C9",
.desc = "MWAIT 0x50",
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 2000,
@ -857,7 +857,7 @@ static struct cpuidle_state bxt_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C10-BXT",
.name = "C10",
.desc = "MWAIT 0x60",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 10000,
@ -870,7 +870,7 @@ static struct cpuidle_state bxt_cstates[] = {
static struct cpuidle_state dnv_cstates[] = {
{
.name = "C1-DNV",
.name = "C1",
.desc = "MWAIT 0x00",
.flags = MWAIT2flg(0x00),
.exit_latency = 2,
@ -878,7 +878,7 @@ static struct cpuidle_state dnv_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C1E-DNV",
.name = "C1E",
.desc = "MWAIT 0x01",
.flags = MWAIT2flg(0x01),
.exit_latency = 10,
@ -886,7 +886,7 @@ static struct cpuidle_state dnv_cstates[] = {
.enter = &intel_idle,
.enter_freeze = intel_idle_freeze, },
{
.name = "C6-DNV",
.name = "C6",
.desc = "MWAIT 0x20",
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 50,

7
include/linux/pm_qos.h
View File

@ -170,6 +170,12 @@ static inline s32 dev_pm_qos_requested_flags(struct device *dev)
{
return dev->power.qos->flags_req->data.flr.flags;
}
static inline s32 dev_pm_qos_raw_read_value(struct device *dev)
{
return IS_ERR_OR_NULL(dev->power.qos) ?
0 : pm_qos_read_value(&dev->power.qos->resume_latency);
}
#else
static inline enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev,
s32 mask)
@ -228,6 +234,7 @@ static inline void dev_pm_qos_hide_latency_tolerance(struct device *dev) {}
static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev) { return 0; }
static inline s32 dev_pm_qos_requested_flags(struct device *dev) { return 0; }
static inline s32 dev_pm_qos_raw_read_value(struct device *dev) { return 0; }
#endif
#endif

93
kernel/power/hibernate.c
View File

@ -10,6 +10,8 @@
* This file is released under the GPLv2.
*/
#define pr_fmt(fmt) "PM: " fmt
#include <linux/export.h>
#include <linux/suspend.h>
#include <linux/syscalls.h>
@ -104,7 +106,7 @@ EXPORT_SYMBOL(system_entering_hibernation);
#ifdef CONFIG_PM_DEBUG
static void hibernation_debug_sleep(void)
{
printk(KERN_INFO "hibernation debug: Waiting for 5 seconds.\n");
pr_info("hibernation debug: Waiting for 5 seconds.\n");
mdelay(5000);
}
@ -250,10 +252,9 @@ void swsusp_show_speed(ktime_t start, ktime_t stop,
centisecs = 1; /* avoid div-by-zero */
k = nr_pages * (PAGE_SIZE / 1024);
kps = (k * 100) / centisecs;
printk(KERN_INFO "PM: %s %u kbytes in %u.%02u seconds (%u.%02u MB/s)\n",
msg, k,
centisecs / 100, centisecs % 100,
kps / 1000, (kps % 1000) / 10);
pr_info("%s %u kbytes in %u.%02u seconds (%u.%02u MB/s)\n",
msg, k, centisecs / 100, centisecs % 100, kps / 1000,
(kps % 1000) / 10);
}
/**
@ -271,8 +272,7 @@ static int create_image(int platform_mode)
error = dpm_suspend_end(PMSG_FREEZE);
if (error) {
printk(KERN_ERR "PM: Some devices failed to power down, "
"aborting hibernation\n");
pr_err("Some devices failed to power down, aborting hibernation\n");
return error;
}
@ -288,8 +288,7 @@ static int create_image(int platform_mode)
error = syscore_suspend();
if (error) {
printk(KERN_ERR "PM: Some system devices failed to power down, "
"aborting hibernation\n");
pr_err("Some system devices failed to power down, aborting hibernation\n");
goto Enable_irqs;
}
@ -304,8 +303,8 @@ static int create_image(int platform_mode)
restore_processor_state();
trace_suspend_resume(TPS("machine_suspend"), PM_EVENT_HIBERNATE, false);
if (error)
printk(KERN_ERR "PM: Error %d creating hibernation image\n",
error);
pr_err("Error %d creating hibernation image\n", error);
if (!in_suspend) {
events_check_enabled = false;
clear_free_pages();
@ -432,8 +431,7 @@ static int resume_target_kernel(bool platform_mode)
error = dpm_suspend_end(PMSG_QUIESCE);
if (error) {
printk(KERN_ERR "PM: Some devices failed to power down, "
"aborting resume\n");
pr_err("Some devices failed to power down, aborting resume\n");
return error;
}
@ -608,6 +606,22 @@ static void power_down(void)
{
#ifdef CONFIG_SUSPEND
int error;
if (hibernation_mode == HIBERNATION_SUSPEND) {
error = suspend_devices_and_enter(PM_SUSPEND_MEM);
if (error) {
hibernation_mode = hibernation_ops ?
HIBERNATION_PLATFORM :
HIBERNATION_SHUTDOWN;
} else {
/* Restore swap signature. */
error = swsusp_unmark();
if (error)
pr_err("Swap will be unusable! Try swapon -a.\n");
return;
}
}
#endif
switch (hibernation_mode) {
@ -620,32 +634,13 @@ static void power_down(void)
if (pm_power_off)
kernel_power_off();
break;
#ifdef CONFIG_SUSPEND
case HIBERNATION_SUSPEND:
error = suspend_devices_and_enter(PM_SUSPEND_MEM);
if (error) {
if (hibernation_ops)
hibernation_mode = HIBERNATION_PLATFORM;
else
hibernation_mode = HIBERNATION_SHUTDOWN;
power_down();
}
/*
* Restore swap signature.
*/
error = swsusp_unmark();
if (error)
printk(KERN_ERR "PM: Swap will be unusable! "
"Try swapon -a.\n");
return;
#endif
}
kernel_halt();
/*
* Valid image is on the disk, if we continue we risk serious data
* corruption after resume.
*/
printk(KERN_CRIT "PM: Please power down manually\n");
pr_crit("Power down manually\n");
while (1)
cpu_relax();
}
@ -655,7 +650,7 @@ static int load_image_and_restore(void)
int error;
unsigned int flags;
pr_debug("PM: Loading hibernation image.\n");
pr_debug("Loading hibernation image.\n");
lock_device_hotplug();
error = create_basic_memory_bitmaps();
@ -667,7 +662,7 @@ static int load_image_and_restore(void)
if (!error)
hibernation_restore(flags & SF_PLATFORM_MODE);
printk(KERN_ERR "PM: Failed to load hibernation image, recovering.\n");
pr_err("Failed to load hibernation image, recovering.\n");
swsusp_free();
free_basic_memory_bitmaps();
Unlock:
@ -685,7 +680,7 @@ int hibernate(void)
bool snapshot_test = false;
if (!hibernation_available()) {
pr_debug("PM: Hibernation not available.\n");
pr_debug("Hibernation not available.\n");
return -EPERM;
}
@ -703,9 +698,9 @@ int hibernate(void)
goto Exit;
}
printk(KERN_INFO "PM: Syncing filesystems ... ");
pr_info("Syncing filesystems ... \n");
sys_sync();
printk("done.\n");
pr_info("done.\n");
error = freeze_processes();
if (error)
@ -731,7 +726,7 @@ int hibernate(void)
else
flags |= SF_CRC32_MODE;
pr_debug("PM: writing image.\n");
pr_debug("Writing image.\n");
error = swsusp_write(flags);
swsusp_free();
if (!error) {
@ -743,7 +738,7 @@ int hibernate(void)
in_suspend = 0;
pm_restore_gfp_mask();
} else {
pr_debug("PM: Image restored successfully.\n");
pr_debug("Image restored successfully.\n");
}
Free_bitmaps:
@ -751,7 +746,7 @@ int hibernate(void)
Thaw:
unlock_device_hotplug();
if (snapshot_test) {
pr_debug("PM: Checking hibernation image\n");
pr_debug("Checking hibernation image\n");
error = swsusp_check();
if (!error)
error = load_image_and_restore();
@ -815,10 +810,10 @@ static int software_resume(void)
goto Unlock;
}
pr_debug("PM: Checking hibernation image partition %s\n", resume_file);
pr_debug("Checking hibernation image partition %s\n", resume_file);
if (resume_delay) {
printk(KERN_INFO "Waiting %dsec before reading resume device...\n",
pr_info("Waiting %dsec before reading resume device ...\n",
resume_delay);
ssleep(resume_delay);
}
@ -857,10 +852,10 @@ static int software_resume(void)
}
Check_image:
pr_debug("PM: Hibernation image partition %d:%d present\n",
pr_debug("Hibernation image partition %d:%d present\n",
MAJOR(swsusp_resume_device), MINOR(swsusp_resume_device));
pr_debug("PM: Looking for hibernation image.\n");
pr_debug("Looking for hibernation image.\n");
error = swsusp_check();
if (error)
goto Unlock;
@ -879,7 +874,7 @@ static int software_resume(void)
goto Close_Finish;
}
pr_debug("PM: Preparing processes for restore.\n");
pr_debug("Preparing processes for restore.\n");
error = freeze_processes();
if (error)
goto Close_Finish;
@ -892,7 +887,7 @@ static int software_resume(void)
/* For success case, the suspend path will release the lock */
Unlock:
mutex_unlock(&pm_mutex);
pr_debug("PM: Hibernation image not present or could not be loaded.\n");
pr_debug("Hibernation image not present or could not be loaded.\n");
return error;
Close_Finish:
swsusp_close(FMODE_READ);
@ -1016,7 +1011,7 @@ static ssize_t disk_store(struct kobject *kobj, struct kobj_attribute *attr,
error = -EINVAL;
if (!error)
pr_debug("PM: Hibernation mode set to '%s'\n",
pr_debug("Hibernation mode set to '%s'\n",
hibernation_modes[mode]);
unlock_system_sleep();
return error ? error : n;
@ -1052,7 +1047,7 @@ static ssize_t resume_store(struct kobject *kobj, struct kobj_attribute *attr,
lock_system_sleep();
swsusp_resume_device = res;
unlock_system_sleep();
printk(KERN_INFO "PM: Starting manual resume from disk\n");
pr_info("Starting manual resume from disk\n");
noresume = 0;
software_resume();
return n;