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forcedeth: add new tx stat counters
This patch adds support for new tx statistic counters in the hardware - unicast, multicast, and broadcast Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Ayaz Abdulla
Jeff Garzik
parent
1ef6841b4c
commit
9c6624352c
@ -77,26 +77,27 @@
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* Hardware access:
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*/
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#define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
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#define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
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#define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
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#define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
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#define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
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#define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
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#define DEV_HAS_MSI 0x00040 /* device supports MSI */
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#define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
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#define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
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#define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
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#define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
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#define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
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#define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
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#define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
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#define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
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#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
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#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
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#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
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#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
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#define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
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#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
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#define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
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#define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
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#define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
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#define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
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#define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
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#define DEV_HAS_MSI 0x000040 /* device supports MSI */
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#define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
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#define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
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#define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
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#define DEV_HAS_STATISTICS_V2 0x000400 /* device supports hw statistics version 2 */
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#define DEV_HAS_STATISTICS_V3 0x000800 /* device supports hw statistics version 3 */
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#define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
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#define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
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#define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
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#define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
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#define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
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#define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
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#define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
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#define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
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#define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
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enum {
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NvRegIrqStatus = 0x000,
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@ -270,6 +271,9 @@ enum {
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#define NVREG_MIICTL_WRITE 0x00400
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#define NVREG_MIICTL_ADDRSHIFT 5
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NvRegMIIData = 0x194,
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NvRegTxUnicast = 0x1a0,
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NvRegTxMulticast = 0x1a4,
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NvRegTxBroadcast = 0x1a8,
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NvRegWakeUpFlags = 0x200,
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#define NVREG_WAKEUPFLAGS_VAL 0x7770
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#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
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@ -618,7 +622,12 @@ static const struct nv_ethtool_str nv_estats_str[] = {
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{ "rx_bytes" },
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{ "tx_pause" },
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{ "rx_pause" },
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{ "rx_drop_frame" }
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{ "rx_drop_frame" },
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/* version 3 stats */
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{ "tx_unicast" },
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{ "tx_multicast" },
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{ "tx_broadcast" }
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};
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struct nv_ethtool_stats {
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@ -654,9 +663,15 @@ struct nv_ethtool_stats {
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u64 tx_pause;
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u64 rx_pause;
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u64 rx_drop_frame;
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/* version 3 stats */
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u64 tx_unicast;
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u64 tx_multicast;
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u64 tx_broadcast;
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};
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#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
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#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
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#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
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#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
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/* diagnostics */
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@ -1630,6 +1645,12 @@ static void nv_get_hw_stats(struct net_device *dev)
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np->estats.rx_pause += readl(base + NvRegRxPause);
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np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
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}
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if (np->driver_data & DEV_HAS_STATISTICS_V3) {
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np->estats.tx_unicast += readl(base + NvRegTxUnicast);
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np->estats.tx_multicast += readl(base + NvRegTxMulticast);
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np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
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}
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}
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/*
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@ -1643,7 +1664,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev)
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struct fe_priv *np = netdev_priv(dev);
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/* If the nic supports hw counters then retrieve latest values */
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if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
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if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
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nv_get_hw_stats(dev);
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/* copy to net_device stats */
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@ -4742,6 +4763,8 @@ static int nv_get_sset_count(struct net_device *dev, int sset)
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return NV_DEV_STATISTICS_V1_COUNT;
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else if (np->driver_data & DEV_HAS_STATISTICS_V2)
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return NV_DEV_STATISTICS_V2_COUNT;
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else if (np->driver_data & DEV_HAS_STATISTICS_V3)
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return NV_DEV_STATISTICS_V3_COUNT;
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else
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return 0;
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default:
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@ -5326,7 +5349,7 @@ static int nv_open(struct net_device *dev)
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mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
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/* start statistics timer */
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if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
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if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
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mod_timer(&np->stats_poll,
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round_jiffies(jiffies + STATS_INTERVAL));
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@ -5430,7 +5453,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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if (err < 0)
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goto out_disable;
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if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
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if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
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np->register_size = NV_PCI_REGSZ_VER3;
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else if (id->driver_data & DEV_HAS_STATISTICS_V1)
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np->register_size = NV_PCI_REGSZ_VER2;
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@ -6085,35 +6108,35 @@ static struct pci_device_id pci_tbl[] = {
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},
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{ /* MCP77 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP77 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP77 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP77 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP79 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP79 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP79 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{ /* MCP79 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
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},
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{0,},
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};
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