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Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King: "A small set of ARM fixes for -rc3, most of them not far off one-liners, with the exception of fixing the V7 cache invalidation for incoming SMP processors which was causing problems for SoCFPGA devices" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: fix __virt_to_idmap build error on !MMU ARM: invalidate L1 before enabling coherency ARM: 8404/1: dma-mapping: fix off-by-one error in bitmap size check ARM: 8402/1: perf: Don't use of_node after putting it ARM: 8400/1: use virt_to_idmap to get phys_reset address
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commit
9d37e6679d
@ -286,7 +286,7 @@ extern phys_addr_t (*arch_virt_to_idmap)(unsigned long x);
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*/
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static inline phys_addr_t __virt_to_idmap(unsigned long x)
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{
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if (arch_virt_to_idmap)
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if (IS_ENABLED(CONFIG_MMU) && arch_virt_to_idmap)
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return arch_virt_to_idmap(x);
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else
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return __virt_to_phys(x);
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@ -818,12 +818,13 @@ static int of_pmu_irq_cfg(struct arm_pmu *pmu)
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if (arch_find_n_match_cpu_physical_id(dn, cpu, NULL))
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break;
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of_node_put(dn);
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if (cpu >= nr_cpu_ids) {
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pr_warn("Failed to find logical CPU for %s\n",
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dn->name);
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of_node_put(dn);
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break;
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}
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of_node_put(dn);
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irqs[i] = cpu;
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cpumask_set_cpu(cpu, &pmu->supported_cpus);
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@ -50,7 +50,7 @@ static void __soft_restart(void *addr)
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flush_cache_all();
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/* Switch to the identity mapping. */
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phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
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phys_reset = (phys_reset_t)(unsigned long)virt_to_idmap(cpu_reset);
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phys_reset((unsigned long)addr);
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/* Should never get here. */
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@ -1971,7 +1971,7 @@ static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
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{
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int next_bitmap;
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if (mapping->nr_bitmaps > mapping->extensions)
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if (mapping->nr_bitmaps >= mapping->extensions)
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return -EINVAL;
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next_bitmap = mapping->nr_bitmaps;
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@ -274,7 +274,10 @@ __v7_ca15mp_setup:
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__v7_b15mp_setup:
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__v7_ca17mp_setup:
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mov r10, #0
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1:
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1: adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
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bl v7_invalidate_l1
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ldmia r12, {r0-r5, lr}
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
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ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
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@ -283,7 +286,7 @@ __v7_ca17mp_setup:
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orreq r0, r0, r10 @ Enable CPU-specific SMP bits
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mcreq p15, 0, r0, c1, c0, 1
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#endif
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b __v7_setup
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b __v7_setup_cont
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/*
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* Errata:
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@ -413,10 +416,11 @@ __v7_pj4b_setup:
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__v7_setup:
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
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bl v7_invalidate_l1
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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ldmia r12, {r0-r5, lr}
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__v7_setup_cont:
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and r0, r9, #0xff000000 @ ARM?
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teq r0, #0x41000000
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bne __errata_finish
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@ -480,7 +484,7 @@ ENDPROC(__v7_setup)
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.align 2
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__v7_setup_stack:
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.space 4 * 11 @ 11 registers
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.space 4 * 7 @ 12 registers
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__INITDATA
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