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arm: sunxi: Revert changes merged through net-next.
This reverts commits2c0cba482e
("arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module") to2428fd0fe5
("arm64: defconfig: Enable dwmac-sun8i driver on defconfig") and3432a86e64
("arm: sun8i: orangepipc: use internal phy-mode") to5a79b4f2a5
("arm: sun8i: orangepi-2: use internal phy-mode") that should be merged through the arm-soc tree, and end up in merge conflicts and build failures. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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f1efece4e2
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@ -57,7 +57,6 @@
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aliases {
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serial0 = &uart0;
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/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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ethernet0 = &emac;
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ethernet1 = &xr819;
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};
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@ -104,13 +103,6 @@
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status = "okay";
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};
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&emac {
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phy-handle = <&int_mii_phy>;
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phy-mode = "internal";
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allwinner,leds-active-low;
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_a>;
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@ -46,10 +46,3 @@
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model = "FriendlyARM NanoPi NEO";
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compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
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};
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&emac {
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phy-handle = <&int_mii_phy>;
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phy-mode = "internal";
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allwinner,leds-active-low;
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status = "okay";
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};
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@ -54,7 +54,6 @@
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aliases {
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serial0 = &uart0;
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/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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ethernet0 = &emac;
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ethernet1 = &rtl8189;
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};
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@ -109,13 +108,6 @@
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status = "okay";
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};
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&emac {
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phy-handle = <&int_mii_phy>;
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phy-mode = "internal";
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allwinner,leds-active-low;
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status = "okay";
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};
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&ir {
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pinctrl-names = "default";
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pinctrl-0 = <&ir_pins_a>;
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@ -52,7 +52,6 @@
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compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
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aliases {
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ethernet0 = &emac;
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serial0 = &uart0;
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};
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@ -98,13 +97,6 @@
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status = "okay";
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};
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&emac {
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phy-handle = <&int_mii_phy>;
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phy-mode = "internal";
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allwinner,leds-active-low;
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
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@ -53,11 +53,6 @@
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};
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};
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&emac {
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/* LEDs changed to active high on the plus */
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/delete-property/ allwinner,leds-active-low;
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_a>;
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@ -52,7 +52,6 @@
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compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
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aliases {
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ethernet0 = &emac;
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serial0 = &uart0;
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};
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@ -110,13 +109,6 @@
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status = "okay";
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};
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&emac {
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phy-handle = <&int_mii_phy>;
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phy-mode = "internal";
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allwinner,leds-active-low;
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status = "okay";
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};
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&ir {
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pinctrl-names = "default";
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pinctrl-0 = <&ir_pins_a>;
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@ -83,12 +83,6 @@
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#size-cells = <1>;
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ranges;
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syscon: syscon@1c00000 {
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compatible = "allwinner,sun8i-h3-system-controller",
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"syscon";
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reg = <0x01c00000 0x1000>;
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};
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun8i-h3-dma";
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reg = <0x01c02000 0x1000>;
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@ -285,14 +279,6 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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emac_rgmii_pins: emac0 {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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"PD12", "PD13", "PD15", "PD16", "PD17";
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function = "emac";
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drive-strength = <40>;
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};
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i2c0_pins: i2c0 {
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pins = "PA11", "PA12";
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function = "i2c0";
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@ -389,32 +375,6 @@
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clocks = <&osc24M>;
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};
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c30000 0x104>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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int_mii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clocks = <&ccu CLK_BUS_EPHY>;
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resets = <&ccu RST_BUS_EPHY>;
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};
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};
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};
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spi0: spi@01c68000 {
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compatible = "allwinner,sun8i-h3-spi";
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reg = <0x01c68000 0x1000>;
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@ -257,7 +257,6 @@ CONFIG_SMSC911X=y
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CONFIG_STMMAC_ETH=y
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CONFIG_STMMAC_PLATFORM=y
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CONFIG_DWMAC_DWC_QOS_ETH=y
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CONFIG_DWMAC_SUN8I=y
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CONFIG_TI_CPSW=y
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CONFIG_XILINX_EMACLITE=y
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CONFIG_AT803X_PHY=y
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@ -40,7 +40,6 @@ CONFIG_ATA=y
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CONFIG_AHCI_SUNXI=y
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CONFIG_NETDEVICES=y
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CONFIG_SUN4I_EMAC=y
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CONFIG_DWMAC_SUN8I=y
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# CONFIG_NET_VENDOR_ARC is not set
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# CONFIG_NET_CADENCE is not set
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# CONFIG_NET_VENDOR_BROADCOM is not set
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@ -67,14 +67,6 @@
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};
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@ -85,13 +77,6 @@
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bias-pull-up;
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};
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&mdio {
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ext_rgmii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@ -46,20 +46,5 @@
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model = "Pine64+";
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compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
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/* TODO: Camera, touchscreen, etc. */
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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status = "okay";
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};
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&mdio {
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ext_rgmii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
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};
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@ -70,15 +70,6 @@
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status = "okay";
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins>;
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phy-mode = "rmii";
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phy-handle = <&ext_rmii_phy1>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@ -89,13 +80,6 @@
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bias-pull-up;
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};
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&mdio {
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ext_rmii_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@ -129,12 +129,6 @@
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#size-cells = <1>;
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ranges;
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syscon: syscon@1c00000 {
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compatible = "allwinner,sun50i-a64-system-controller",
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"syscon";
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reg = <0x01c00000 0x1000>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -287,21 +281,6 @@
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bias-pull-up;
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};
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rmii_pins: rmii_pins {
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pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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"PD18", "PD19", "PD20", "PD22", "PD23";
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function = "emac";
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drive-strength = <40>;
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};
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rgmii_pins: rgmii_pins {
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pins = "PD8", "PD9", "PD10", "PD11", "PD12",
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"PD13", "PD15", "PD16", "PD17", "PD18",
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"PD19", "PD20", "PD21", "PD22", "PD23";
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function = "emac";
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drive-strength = <40>;
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};
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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@ -406,26 +385,6 @@
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#size-cells = <0>;
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};
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun50i-a64-emac";
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syscon = <&syscon>;
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reg = <0x01c30000 0x100>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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@ -191,7 +191,6 @@ CONFIG_RAVB=y
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CONFIG_SMC91X=y
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CONFIG_SMSC911X=y
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CONFIG_STMMAC_ETH=m
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CONFIG_DWMAC_SUN8I=m
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CONFIG_MDIO_BUS_MUX_MMIOREG=y
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CONFIG_MESON_GXL_PHY=m
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CONFIG_MICREL_PHY=y
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