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ARM: bcm2835: Add devicetree for the Raspberry Pi 3.
While this devicetree also works for booting in 32-bit mode, it's placed in arm64 since it's a 64-bit CPU (as suggested by Arnd). Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> (v1) Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
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dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
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dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
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arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
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arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
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/dts-v1/;
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#include "bcm2837.dtsi"
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#include "../../../../arm/boot/dts/bcm2835-rpi.dtsi"
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/ {
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compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
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model = "Raspberry Pi 3 Model B";
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memory {
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reg = <0 0x40000000>;
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};
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leds {
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act {
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gpios = <&gpio 47 0>;
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};
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pwr {
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label = "PWR";
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gpios = <&gpio 35 0>;
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default-state = "keep";
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linux,default-trigger = "default-on";
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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arch/arm64/boot/dts/broadcom/bcm2837.dtsi
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arch/arm64/boot/dts/broadcom/bcm2837.dtsi
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#include "../../../../arm/boot/dts/bcm283x.dtsi"
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/ {
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compatible = "brcm,bcm2836";
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soc {
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ranges = <0x7e000000 0x3f000000 0x1000000>,
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<0x40000000 0x40000000 0x00001000>;
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dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
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local_intc: local_intc {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&local_intc>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&local_intc>;
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interrupts = <0>, // PHYS_SECURE_PPI
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<1>, // PHYS_NONSECURE_PPI
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<3>, // VIRT_PPI
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<2>; // HYP_PPI
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always-on;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000d8>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e8>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000f0>;
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};
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};
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};
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/* Make the BCM2835-style global interrupt controller be a child of the
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* CPU-local interrupt controller.
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*/
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&intc {
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compatible = "brcm,bcm2836-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-parent = <&local_intc>;
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interrupts = <8>;
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};
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