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staging: et131x: Use pci_dev->pcie_mpss and pcie_set_readrq() to simplify code

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The PCI core caches the "PCIe Max Payload Size Supported" in
pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword().
Also use pcie_set_readrq() instead of pcie_capability_clear_and_set_word()
to simplify code.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Mark Einon <mark.einon@gmail.com>
This commit is contained in:
Yijing Wang 2013-09-09 21:13:07 +08:00 committed by Bjorn Helgaas
parent 03078633a6
commit 9db008d0d9
1 changed files with 3 additions and 11 deletions
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14
drivers/staging/et131x/et131x.c
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@ -3605,17 +3605,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
goto err_out;
}
/* Let's set up the PORT LOGIC Register. First we need to know what
* the max_payload_size is
*/
if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
dev_err(&pdev->dev,
"Could not read PCI config space for Max Payload Size\n");
goto err_out;
}
/* Let's set up the PORT LOGIC Register. */
/* Program the Ack/Nak latency and replay timers */
max_payload &= 0x07;
max_payload = pdev->pcie_mpss;
if (max_payload < 2) {
static const u16 acknak[2] = { 0x76, 0xD0 };
@ -3645,8 +3638,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
}
/* Change the max read size to 2k */
if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
if (pcie_set_readrq(pdev, 2048)) {
dev_err(&pdev->dev,
"Couldn't change PCI config space for Max read size\n");
goto err_out;