FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2024-12-17 22:41:25 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: shmobile: wait for MSTP clock status to toggle, when enabling it

Browse Source 
On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically
enable and disable peripheral clocks. To make sure the clock has really
started we have to read back its status register until it confirms success.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Guennadi Liakhovetski 2013-12-14 16:23:51 +01:00 committed by Simon Horman
parent 38dbfb59d1
commit a028c6da34
2 changed files with 50 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/sh/clk/cpg.c
View File

@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)
iowrite32(value, clk->mapped_reg);
}
static unsigned int r8(const void __iomem *addr)
{
return ioread8(addr);
}
static unsigned int r16(const void __iomem *addr)
{
return ioread16(addr);
}
static unsigned int r32(const void __iomem *addr)
{
return ioread32(addr);
}
static int sh_clk_mstp_enable(struct clk *clk)
{
sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
if (clk->status_reg) {
unsigned int (*read)(const void __iomem *addr);
int i;
void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
(phys_addr_t)clk->enable_reg + clk->mapped_reg;
if (clk->flags & CLK_ENABLE_REG_8BIT)
read = r8;
else if (clk->flags & CLK_ENABLE_REG_16BIT)
read = r16;
else
read = r32;
for (i = 1000;
(read(mapped_status) & (1 << clk->enable_bit)) && i;
i--)
cpu_relax();
if (!i) {
pr_err("cpg: failed to enable %p[%d]\n",
clk->enable_reg, clk->enable_bit);
return -ETIMEDOUT;
}
}
return 0;
}

19
include/linux/sh_clk.h
View File

@ -52,6 +52,7 @@ struct clk {
unsigned long flags;
void __iomem *enable_reg;
void __iomem *status_reg;
unsigned int enable_bit;
void __iomem *mapped_reg;
@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target,
unsigned long *best_freq, unsigned long *parent_freq,
unsigned int div_min, unsigned int div_max);
#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
{ \
.parent = _parent, \
.enable_reg = (void __iomem *)_enable_reg, \
.enable_bit = _enable_bit, \
.status_reg = _status_reg, \
.flags = _flags, \
}
#define SH_CLK_MSTP32(_p, _r, _b, _f) \
SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
#define SH_CLK_MSTP32(_p, _r, _b, _f) \
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
#define SH_CLK_MSTP16(_p, _r, _b, _f) \
SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
#define SH_CLK_MSTP8(_p, _r, _b, _f) \
SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
#define SH_CLK_MSTP16(_p, _r, _b, _f) \
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
#define SH_CLK_MSTP8(_p, _r, _b, _f) \
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
int sh_clk_mstp_register(struct clk *clks, int nr);