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https://github.com/FEX-Emu/linux.git
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IB/qib: New SERDES init routine and improvements to SI quality
Implement new SERDES initialization routine and improvements to signal integrity -- disable LE1 adaptation, disable LOS after link-up, set better SERDES parameters. Signed-off-by: Mike Marciniszyn <mike.marciniszyn@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Mike Marciniszyn
Roland Dreier
parent
16028f2777
commit
a0a234d47d
@ -71,6 +71,9 @@ static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
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static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
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static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
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static void serdes_7322_los_enable(struct qib_pportdata *, int);
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static int serdes_7322_init_old(struct qib_pportdata *);
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static int serdes_7322_init_new(struct qib_pportdata *);
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#define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
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@ -1692,6 +1695,8 @@ static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
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(ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
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force_h1(ppd);
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ppd->cpspec->qdr_reforce = 1;
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if (!ppd->dd->cspec->r1)
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serdes_7322_los_enable(ppd, 0);
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} else if (ppd->cpspec->qdr_reforce &&
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(ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
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(ibclt == IB_7322_LT_STATE_CFGENH ||
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@ -1707,15 +1712,32 @@ static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
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ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
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adj_tx_serdes(ppd);
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if (!ppd->cpspec->qdr_dfe_on && ibclt != IB_7322_LT_STATE_LINKUP &&
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ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
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ppd->cpspec->qdr_dfe_on = 1;
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ppd->cpspec->qdr_dfe_time = 0;
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/* On link down, reenable QDR adaptation */
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qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
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ppd->dd->cspec->r1 ?
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QDR_STATIC_ADAPT_DOWN_R1 :
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QDR_STATIC_ADAPT_DOWN);
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if (ibclt != IB_7322_LT_STATE_LINKUP) {
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u8 ltstate = qib_7322_phys_portstate(ibcst);
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u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
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LinkTrainingState);
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if (!ppd->dd->cspec->r1 &&
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pibclt == IB_7322_LT_STATE_LINKUP &&
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ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
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ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
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ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
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ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
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/* If the link went down (but no into recovery,
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* turn LOS back on */
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serdes_7322_los_enable(ppd, 1);
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if (!ppd->cpspec->qdr_dfe_on &&
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ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
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ppd->cpspec->qdr_dfe_on = 1;
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ppd->cpspec->qdr_dfe_time = 0;
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/* On link down, reenable QDR adaptation */
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qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
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ppd->dd->cspec->r1 ?
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QDR_STATIC_ADAPT_DOWN_R1 :
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QDR_STATIC_ADAPT_DOWN);
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printk(KERN_INFO QIB_DRV_NAME
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" IB%u:%u re-enabled QDR adaptation "
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"ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
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}
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}
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}
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@ -5544,7 +5566,7 @@ static void qsfp_7322_event(struct work_struct *work)
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u64 now = get_jiffies_64();
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if (time_after64(now, pwrup))
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break;
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msleep(1);
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msleep(20);
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}
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ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
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/*
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@ -6519,7 +6541,7 @@ static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
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/* make sure we see an updated copy next time around */
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sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
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sleeps++;
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msleep(1);
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msleep(20);
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}
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switch (which) {
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@ -7234,9 +7256,30 @@ static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
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}
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}
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static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
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{
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u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
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printk(KERN_INFO QIB_DRV_NAME " Turning LOS %s for port %d\n",
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(enable ? "on" : "off"), ppd->port);
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if (enable)
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data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
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else
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data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
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qib_write_kreg_port(ppd, krp_serdesctrl, data);
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}
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static int serdes_7322_init(struct qib_pportdata *ppd)
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{
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u64 data;
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int ret = 0;
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if (ppd->dd->cspec->r1)
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ret = serdes_7322_init_old(ppd);
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else
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ret = serdes_7322_init_new(ppd);
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return ret;
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}
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static int serdes_7322_init_old(struct qib_pportdata *ppd)
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{
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u32 le_val;
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/*
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@ -7294,9 +7337,7 @@ static int serdes_7322_init(struct qib_pportdata *ppd)
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ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
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ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
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data = qib_read_kreg_port(ppd, krp_serdesctrl);
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qib_write_kreg_port(ppd, krp_serdesctrl, data |
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SYM_MASK(IBSerdesCtrl_0, RXLOSEN));
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serdes_7322_los_enable(ppd, 1);
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/* rxbistena; set 0 to avoid effects of it switch later */
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ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
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@ -7336,6 +7377,205 @@ static int serdes_7322_init(struct qib_pportdata *ppd)
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return 0;
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}
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static int serdes_7322_init_new(struct qib_pportdata *ppd)
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{
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u64 tstart;
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u32 le_val, rxcaldone;
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int chan, chan_done = (1 << SERDES_CHANS) - 1;
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/*
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* Initialize the Tx DDS tables. Also done every QSFP event,
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* for adapters with QSFP
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*/
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init_txdds_table(ppd, 0);
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/* Clear cmode-override, may be set from older driver */
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
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/* ensure no tx overrides from earlier driver loads */
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qib_write_kreg_port(ppd, krp_tx_deemph_override,
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SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
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reset_tx_deemphasis_override));
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/* START OF LSI SUGGESTED SERDES BRINGUP */
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/* Reset - Calibration Setup */
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/* Stop DFE adaptaion */
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ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
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/* Disable LE1 */
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ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
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/* Disable autoadapt for LE1 */
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ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
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/* Disable LE2 */
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ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
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/* Disable VGA */
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ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
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/* Disable AFE Offset Cancel */
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ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
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/* Disable Timing Loop */
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ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
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/* Disable Frequency Loop */
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ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
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/* Disable Baseline Wander Correction */
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ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
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/* Disable RX Calibration */
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ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
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/* Disable RX Offset Calibration */
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ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
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/* Select BB CDR */
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ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
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/* CDR Step Size */
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ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
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/* Enable phase Calibration */
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ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
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/* DFE Bandwidth [2:14-12] */
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ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
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/* DFE Config (4 taps only) */
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ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
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/* Gain Loop Bandwidth */
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if (!ppd->dd->cspec->r1) {
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ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
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ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
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} else {
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ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
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}
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/* Baseline Wander Correction Gain [13:4-0] (leave as default) */
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/* Baseline Wander Correction Gain [3:7-5] (leave as default) */
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/* Data Rate Select [5:7-6] (leave as default) */
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/* RX Parralel Word Width [3:10-8] (leave as default) */
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/* RX REST */
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/* Single- or Multi-channel reset */
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/* RX Analog reset */
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/* RX Digital reset */
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ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
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msleep(20);
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/* RX Analog reset */
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ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
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msleep(20);
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/* RX Digital reset */
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ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
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msleep(20);
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/* setup LoS params; these are subsystem, so chan == 5 */
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/* LoS filter threshold_count on, ch 0-3, set to 8 */
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
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/* LoS filter threshold_count off, ch 0-3, set to 4 */
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
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/* LoS filter select enabled */
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ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
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/* LoS target data: SDR=4, DDR=2, QDR=1 */
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ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
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ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
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ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
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/* Turn on LOS on initial SERDES init */
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serdes_7322_los_enable(ppd, 1);
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/* FLoop LOS gate: PPM filter enabled */
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ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
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/* RX LATCH CALIBRATION */
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/* Enable Eyefinder Phase Calibration latch */
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ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
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/* Enable RX Offset Calibration latch */
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ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
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msleep(20);
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/* Start Calibration */
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ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
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tstart = get_jiffies_64();
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while (chan_done &&
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!time_after64(tstart, tstart + msecs_to_jiffies(500))) {
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msleep(20);
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for (chan = 0; chan < SERDES_CHANS; ++chan) {
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rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
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(chan + (chan >> 1)),
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25, 0, 0);
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if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
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(~chan_done & (1 << chan)) == 0)
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chan_done &= ~(1 << chan);
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}
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}
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if (chan_done) {
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printk(KERN_INFO QIB_DRV_NAME
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" Serdes %d calibration not done after .5 sec: 0x%x\n",
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IBSD(ppd->hw_pidx), chan_done);
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} else {
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for (chan = 0; chan < SERDES_CHANS; ++chan) {
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rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
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(chan + (chan >> 1)),
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25, 0, 0);
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if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
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printk(KERN_INFO QIB_DRV_NAME
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" Serdes %d chan %d calibration "
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"failed\n", IBSD(ppd->hw_pidx), chan);
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}
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}
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/* Turn off Calibration */
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ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
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msleep(20);
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/* BRING RX UP */
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/* Set LE2 value (May be overridden in qsfp_7322_event) */
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le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
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ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
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/* Set LE2 Loop bandwidth */
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ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
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/* Enable LE2 */
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ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
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msleep(20);
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/* Enable H0 only */
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ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
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/* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
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le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
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ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
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/* Enable VGA */
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ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
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msleep(20);
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/* Set Frequency Loop Bandwidth */
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ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
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/* Enable Frequency Loop */
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ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
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/* Set Timing Loop Bandwidth */
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ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
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/* Enable Timing Loop */
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ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
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msleep(50);
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/* Enable DFE
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* Set receive adaptation mode. SDR and DDR adaptation are
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* always on, and QDR is initially enabled; later disabled.
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*/
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qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
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qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
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qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
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ppd->dd->cspec->r1 ?
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QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
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ppd->cpspec->qdr_dfe_on = 1;
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/* Disable LE1 */
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ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
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/* Disable auto adapt for LE1 */
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ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
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msleep(20);
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/* Enable AFE Offset Cancel */
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ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
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/* Enable Baseline Wander Correction */
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ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
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/* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
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ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
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/* VGA output common mode */
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ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
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return 0;
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}
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/* start adjust QMH serdes parameters */
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static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
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