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ARM: mach-shmobile: Use common INTC IRQ code on sh73a0
Improve IRQ triggering support by making use of the macro INTC_IRQ_PINS_32() for INTCA on sh73a0. Unfortunately it is not as easy as just using the macro as-is, we need to do mask and unmaks in the GIC but configure other bits and ack in INTCA. Update GPIO IRQ mappings while at it. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
da5713ef03
commit
a1993055ef
@ -22,6 +22,7 @@
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/sh_intc.h>
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#include <mach/intc.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -255,20 +256,141 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
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return 0; /* always allow wakeup */
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}
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#define RELOC_BASE 0x1000
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/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
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#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
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INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
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INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
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static int to_gic_irq(struct irq_data *data)
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{
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unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
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if (vect >= 0x3200)
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vect -= 0x3000;
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else
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vect -= 0x0200;
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return gic_spi((vect >> 5) + 1);
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}
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static int to_intca_reloc_irq(struct irq_data *data)
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{
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return data->irq + (RELOC_BASE >> 5);
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}
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#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
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#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
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static void intca_gic_enable(struct irq_data *data)
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{
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irq_cb(irq_unmask, to_intca_reloc_irq(data));
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irq_cb(irq_unmask, to_gic_irq(data));
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}
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static void intca_gic_disable(struct irq_data *data)
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{
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irq_cb(irq_mask, to_gic_irq(data));
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irq_cb(irq_mask, to_intca_reloc_irq(data));
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}
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static void intca_gic_mask_ack(struct irq_data *data)
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{
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irq_cb(irq_mask, to_gic_irq(data));
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irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
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}
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static void intca_gic_eoi(struct irq_data *data)
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{
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irq_cb(irq_eoi, to_gic_irq(data));
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}
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static int intca_gic_set_type(struct irq_data *data, unsigned int type)
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{
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return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
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}
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static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
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{
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return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
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}
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#ifdef CONFIG_SMP
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static int intca_gic_set_affinity(struct irq_data *data,
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const struct cpumask *cpumask,
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bool force)
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{
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return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
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}
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#endif
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struct irq_chip intca_gic_irq_chip = {
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.name = "INTCA-GIC",
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.irq_mask = intca_gic_disable,
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.irq_unmask = intca_gic_enable,
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.irq_mask_ack = intca_gic_mask_ack,
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.irq_eoi = intca_gic_eoi,
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.irq_enable = intca_gic_enable,
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.irq_disable = intca_gic_disable,
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.irq_shutdown = intca_gic_disable,
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.irq_set_type = intca_gic_set_type,
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.irq_set_wake = intca_gic_set_wake,
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#ifdef CONFIG_SMP
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.irq_set_affinity = intca_gic_set_affinity,
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#endif
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};
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static int to_intc_vect(int irq)
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{
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unsigned int irq_pin = irq - gic_spi(1);
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unsigned int offs;
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if (irq_pin < 16)
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offs = 0x0200;
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else
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offs = 0x3000;
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return offs + (irq_pin << 5);
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}
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static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
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{
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generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
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return IRQ_HANDLED;
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}
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static struct irqaction sh73a0_irq_pin_cascade[32];
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void __init sh73a0_init_irq(void)
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{
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void __iomem *gic_dist_base = __io(0xf0001000);
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void __iomem *gic_cpu_base = __io(0xf0000100);
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void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
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int k, n;
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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gic_arch_extn.irq_set_wake = sh73a0_set_wake;
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register_intc_controller(&intcs_desc);
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register_intc_controller(&intca_irq_pins_desc);
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/* demux using INTEVTSA */
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sh73a0_intcs_cascade.name = "INTCS cascade";
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sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
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sh73a0_intcs_cascade.dev_id = intevtsa;
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setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
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/* IRQ pins require special handling through INTCA and GIC */
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for (k = 0; k < 32; k++) {
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sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
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sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
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setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
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n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
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irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
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handle_level_irq, "level");
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set_irq_flags(n, IRQF_VALID); /* yuck */
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}
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}
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@ -2766,41 +2766,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
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{ },
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};
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#define EXT_IRQ(n) gic_spi((n) + 1) /* GIC SPI starting from 1 for IRQ0 */
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/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
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#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
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#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
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static struct pinmux_irq pinmux_irqs[] = {
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PINMUX_IRQ(EXT_IRQ(19), PORT9_FN0),
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PINMUX_IRQ(EXT_IRQ(1), PORT10_FN0),
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PINMUX_IRQ(EXT_IRQ(0), PORT11_FN0),
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PINMUX_IRQ(EXT_IRQ(18), PORT13_FN0),
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PINMUX_IRQ(EXT_IRQ(20), PORT14_FN0),
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PINMUX_IRQ(EXT_IRQ(21), PORT15_FN0),
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PINMUX_IRQ(EXT_IRQ(31), PORT26_FN0),
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PINMUX_IRQ(EXT_IRQ(30), PORT27_FN0),
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PINMUX_IRQ(EXT_IRQ(29), PORT28_FN0),
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PINMUX_IRQ(EXT_IRQ(22), PORT40_FN0),
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PINMUX_IRQ(EXT_IRQ(23), PORT53_FN0),
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PINMUX_IRQ(EXT_IRQ(10), PORT54_FN0),
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PINMUX_IRQ(EXT_IRQ(9), PORT56_FN0),
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PINMUX_IRQ(EXT_IRQ(26), PORT115_FN0),
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PINMUX_IRQ(EXT_IRQ(27), PORT116_FN0),
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PINMUX_IRQ(EXT_IRQ(28), PORT117_FN0),
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PINMUX_IRQ(EXT_IRQ(24), PORT118_FN0),
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PINMUX_IRQ(EXT_IRQ(6), PORT147_FN0),
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PINMUX_IRQ(EXT_IRQ(2), PORT149_FN0),
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PINMUX_IRQ(EXT_IRQ(7), PORT150_FN0),
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PINMUX_IRQ(EXT_IRQ(12), PORT156_FN0),
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PINMUX_IRQ(EXT_IRQ(4), PORT159_FN0),
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PINMUX_IRQ(EXT_IRQ(25), PORT164_FN0),
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PINMUX_IRQ(EXT_IRQ(8), PORT223_FN0),
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PINMUX_IRQ(EXT_IRQ(3), PORT224_FN0),
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PINMUX_IRQ(EXT_IRQ(5), PORT227_FN0),
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PINMUX_IRQ(EXT_IRQ(17), PORT234_FN0),
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PINMUX_IRQ(EXT_IRQ(11), PORT238_FN0),
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PINMUX_IRQ(EXT_IRQ(13), PORT239_FN0),
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PINMUX_IRQ(EXT_IRQ(16), PORT249_FN0),
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PINMUX_IRQ(EXT_IRQ(14), PORT251_FN0),
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PINMUX_IRQ(EXT_IRQ(9), PORT308_FN0),
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PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
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PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
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PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
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PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
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PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
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PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
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PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
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PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
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PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
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PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
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PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
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PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
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PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
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PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
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PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
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PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
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PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
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PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
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PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
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PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
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PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
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PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
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PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
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PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
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PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
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PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
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PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
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PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
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PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
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PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
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PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
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PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
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};
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static struct pinmux_info sh73a0_pinmux_info = {
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