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ASoC: sta32x: Convert to direct regmap API usage.
use the regmap API directly rather than relying on the snd_soc_read/write functions as this seems to be in accordance with common practice. Signed-off-by: Thomas Niederprüm <niederp@physik.uni-kl.de> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Thomas Niederprüm
Mark Brown
parent
97bf6af1f9
commit
a1be4cead9
@ -581,6 +581,7 @@ config SND_SOC_SSM4567
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config SND_SOC_STA32X
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tristate
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select REGMAP_I2C
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config SND_SOC_STA350
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tristate "STA350 speaker amplifier"
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@ -102,6 +102,35 @@ static const struct reg_default sta32x_regs[] = {
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{ 0x2c, 0x0c },
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};
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static const struct regmap_range sta32x_write_regs_range[] = {
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regmap_reg_range(STA32X_CONFA, STA32X_AUTO2),
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regmap_reg_range(STA32X_C1CFG, STA32X_FDRC2),
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};
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static const struct regmap_range sta32x_read_regs_range[] = {
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regmap_reg_range(STA32X_CONFA, STA32X_AUTO2),
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regmap_reg_range(STA32X_C1CFG, STA32X_FDRC2),
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};
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static const struct regmap_range sta32x_volatile_regs_range[] = {
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regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
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};
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static const struct regmap_access_table sta32x_write_regs = {
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.yes_ranges = sta32x_write_regs_range,
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.n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range),
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};
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static const struct regmap_access_table sta32x_read_regs = {
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.yes_ranges = sta32x_read_regs_range,
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.n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range),
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};
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static const struct regmap_access_table sta32x_volatile_regs = {
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.yes_ranges = sta32x_volatile_regs_range,
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.n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range),
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};
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/* regulator power supply names */
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static const char *sta32x_supply_names[] = {
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"Vdda", /* analog supply, 3.3VV */
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@ -122,6 +151,7 @@ struct sta32x_priv {
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u32 coef_shadow[STA32X_COEF_COUNT];
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struct delayed_work watchdog_work;
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int shutdown;
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struct mutex coeff_lock;
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};
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static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
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@ -244,29 +274,42 @@ static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
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int numcoef = kcontrol->private_value >> 16;
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int index = kcontrol->private_value & 0xffff;
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unsigned int cfud;
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int i;
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unsigned int cfud, val;
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int i, ret = 0;
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mutex_lock(&sta32x->coeff_lock);
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/* preserve reserved bits in STA32X_CFUD */
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cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
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/* chip documentation does not say if the bits are self clearing,
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* so do it explicitly */
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snd_soc_write(codec, STA32X_CFUD, cfud);
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regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
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cfud &= 0xf0;
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/*
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* chip documentation does not say if the bits are self clearing,
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* so do it explicitly
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*/
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
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snd_soc_write(codec, STA32X_CFADDR2, index);
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if (numcoef == 1)
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x04);
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else if (numcoef == 5)
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x08);
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else
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return -EINVAL;
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for (i = 0; i < 3 * numcoef; i++)
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ucontrol->value.bytes.data[i] =
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snd_soc_read(codec, STA32X_B1CF1 + i);
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regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
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if (numcoef == 1) {
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
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} else if (numcoef == 5) {
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
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} else {
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ret = -EINVAL;
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goto exit_unlock;
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}
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return 0;
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for (i = 0; i < 3 * numcoef; i++) {
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regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
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ucontrol->value.bytes.data[i] = val;
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}
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exit_unlock:
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mutex_unlock(&sta32x->coeff_lock);
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return ret;
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}
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static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
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@ -280,24 +323,27 @@ static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
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int i;
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/* preserve reserved bits in STA32X_CFUD */
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cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
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/* chip documentation does not say if the bits are self clearing,
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* so do it explicitly */
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snd_soc_write(codec, STA32X_CFUD, cfud);
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regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
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cfud &= 0xf0;
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/*
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* chip documentation does not say if the bits are self clearing,
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* so do it explicitly
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*/
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
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snd_soc_write(codec, STA32X_CFADDR2, index);
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regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
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for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
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sta32x->coef_shadow[index + i] =
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(ucontrol->value.bytes.data[3 * i] << 16)
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| (ucontrol->value.bytes.data[3 * i + 1] << 8)
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for (i = 0; i < 3 * numcoef; i++)
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snd_soc_write(codec, STA32X_B1CF1 + i,
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ucontrol->value.bytes.data[i]);
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regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
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ucontrol->value.bytes.data[i]);
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if (numcoef == 1)
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
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else if (numcoef == 5)
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x02);
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
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else
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return -EINVAL;
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@ -311,20 +357,23 @@ static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec)
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int i;
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/* preserve reserved bits in STA32X_CFUD */
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cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
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regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
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cfud &= 0xf0;
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for (i = 0; i < STA32X_COEF_COUNT; i++) {
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snd_soc_write(codec, STA32X_CFADDR2, i);
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snd_soc_write(codec, STA32X_B1CF1,
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(sta32x->coef_shadow[i] >> 16) & 0xff);
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snd_soc_write(codec, STA32X_B1CF2,
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(sta32x->coef_shadow[i] >> 8) & 0xff);
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snd_soc_write(codec, STA32X_B1CF3,
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(sta32x->coef_shadow[i]) & 0xff);
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/* chip documentation does not say if the bits are
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* self-clearing, so do it explicitly */
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snd_soc_write(codec, STA32X_CFUD, cfud);
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snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
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regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
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regmap_write(sta32x->regmap, STA32X_B1CF1,
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(sta32x->coef_shadow[i] >> 16) & 0xff);
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regmap_write(sta32x->regmap, STA32X_B1CF2,
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(sta32x->coef_shadow[i] >> 8) & 0xff);
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regmap_write(sta32x->regmap, STA32X_B1CF3,
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(sta32x->coef_shadow[i]) & 0xff);
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/*
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* chip documentation does not say if the bits are
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* self-clearing, so do it explicitly
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*/
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
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regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
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}
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return 0;
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}
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@ -336,11 +385,11 @@ static int sta32x_cache_sync(struct snd_soc_codec *codec)
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int rc;
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/* mute during register sync */
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mute = snd_soc_read(codec, STA32X_MMUTE);
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snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
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regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
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regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
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sta32x_sync_coef_shadow(codec);
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rc = regcache_sync(sta32x->regmap);
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snd_soc_write(codec, STA32X_MMUTE, mute);
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regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
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return rc;
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}
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@ -599,10 +648,7 @@ static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
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u8 confb = snd_soc_read(codec, STA32X_CONFB);
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pr_debug("\n");
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confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM);
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u8 confb = 0;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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@ -632,8 +678,8 @@ static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
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return -EINVAL;
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}
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snd_soc_write(codec, STA32X_CONFB, confb);
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return 0;
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return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
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STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
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}
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/**
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@ -653,7 +699,7 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream,
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struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
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unsigned int rate;
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int i, mcs = -1, ir = -1;
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u8 confa, confb;
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unsigned int confa, confb;
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rate = params_rate(params);
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pr_debug("rate: %u\n", rate);
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@ -672,12 +718,10 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream,
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if (mcs < 0)
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return -EINVAL;
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confa = snd_soc_read(codec, STA32X_CONFA);
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confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK);
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confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT);
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confa = (ir << STA32X_CONFA_IR_SHIFT) |
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(mcs << STA32X_CONFA_MCS_SHIFT);
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confb = 0;
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confb = snd_soc_read(codec, STA32X_CONFB);
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confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB);
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switch (params_width(params)) {
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case 24:
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pr_debug("24bit\n");
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@ -746,8 +790,20 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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snd_soc_write(codec, STA32X_CONFA, confa);
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snd_soc_write(codec, STA32X_CONFB, confb);
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ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
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STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
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confa);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
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STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
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confb);
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if (ret < 0)
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return ret;
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return 0;
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}
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return 0;
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}
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@ -773,7 +829,7 @@ static int sta32x_set_bias_level(struct snd_soc_codec *codec,
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case SND_SOC_BIAS_PREPARE:
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/* Full power on */
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snd_soc_update_bits(codec, STA32X_CONFF,
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regmap_update_bits(sta32x->regmap, STA32X_CONFF,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
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break;
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@ -792,19 +848,17 @@ static int sta32x_set_bias_level(struct snd_soc_codec *codec,
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sta32x_watchdog_start(sta32x);
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}
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/* Power up to mute */
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/* FIXME */
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snd_soc_update_bits(codec, STA32X_CONFF,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
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/* Power down */
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regmap_update_bits(sta32x->regmap, STA32X_CONFF,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
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0);
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break;
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case SND_SOC_BIAS_OFF:
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/* The chip runs through the power down sequence for us. */
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snd_soc_update_bits(codec, STA32X_CONFF,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
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STA32X_CONFF_PWDN);
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regmap_update_bits(sta32x->regmap, STA32X_CONFF,
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STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
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msleep(300);
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sta32x_watchdog_stop(sta32x);
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regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
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@ -836,11 +890,8 @@ static struct snd_soc_dai_driver sta32x_dai = {
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static int sta32x_probe(struct snd_soc_codec *codec)
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{
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struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
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struct sta32x_platform_data *pdata = sta32x->pdata;
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int i, ret = 0, thermal = 0;
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sta32x->codec = codec;
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sta32x->pdata = dev_get_platdata(codec->dev);
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ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
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sta32x->supplies);
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if (ret != 0) {
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@ -848,50 +899,34 @@ static int sta32x_probe(struct snd_soc_codec *codec)
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return ret;
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}
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/* Chip documentation explicitly requires that the reset values
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* of reserved register bits are left untouched.
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* Write the register default value to cache for reserved registers,
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* so the write to the these registers are suppressed by the cache
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* restore code when it skips writes of default registers.
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*/
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regcache_cache_only(sta32x->regmap, true);
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snd_soc_write(codec, STA32X_CONFC, 0xc2);
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snd_soc_write(codec, STA32X_CONFE, 0xc2);
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snd_soc_write(codec, STA32X_CONFF, 0x5c);
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snd_soc_write(codec, STA32X_MMUTE, 0x10);
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snd_soc_write(codec, STA32X_AUTO1, 0x60);
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snd_soc_write(codec, STA32X_AUTO3, 0x00);
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snd_soc_write(codec, STA32X_C3CFG, 0x40);
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regcache_cache_only(sta32x->regmap, false);
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/* set thermal warning adjustment and recovery */
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if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE))
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if (!pdata->thermal_warning_recovery)
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thermal |= STA32X_CONFA_TWAB;
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if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE))
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if (!pdata->thermal_warning_adjustment)
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thermal |= STA32X_CONFA_TWRB;
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snd_soc_update_bits(codec, STA32X_CONFA,
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STA32X_CONFA_TWAB | STA32X_CONFA_TWRB,
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thermal);
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regmap_update_bits(sta32x->regmap, STA32X_CONFA,
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STA32X_CONFA_TWAB | STA32X_CONFA_TWRB,
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thermal);
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/* select output configuration */
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snd_soc_update_bits(codec, STA32X_CONFF,
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STA32X_CONFF_OCFG_MASK,
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sta32x->pdata->output_conf
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<< STA32X_CONFF_OCFG_SHIFT);
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regmap_update_bits(sta32x->regmap, STA32X_CONFF,
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STA32X_CONFF_OCFG_MASK,
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pdata->output_conf
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<< STA32X_CONFF_OCFG_SHIFT);
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/* channel to output mapping */
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snd_soc_update_bits(codec, STA32X_C1CFG,
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STA32X_CxCFG_OM_MASK,
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sta32x->pdata->ch1_output_mapping
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<< STA32X_CxCFG_OM_SHIFT);
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snd_soc_update_bits(codec, STA32X_C2CFG,
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STA32X_CxCFG_OM_MASK,
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sta32x->pdata->ch2_output_mapping
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<< STA32X_CxCFG_OM_SHIFT);
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snd_soc_update_bits(codec, STA32X_C3CFG,
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STA32X_CxCFG_OM_MASK,
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sta32x->pdata->ch3_output_mapping
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<< STA32X_CxCFG_OM_SHIFT);
|
||||
regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
|
||||
STA32X_CxCFG_OM_MASK,
|
||||
pdata->ch1_output_mapping
|
||||
<< STA32X_CxCFG_OM_SHIFT);
|
||||
regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
|
||||
STA32X_CxCFG_OM_MASK,
|
||||
pdata->ch2_output_mapping
|
||||
<< STA32X_CxCFG_OM_SHIFT);
|
||||
regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
|
||||
STA32X_CxCFG_OM_MASK,
|
||||
pdata->ch3_output_mapping
|
||||
<< STA32X_CxCFG_OM_SHIFT);
|
||||
|
||||
/* initialize coefficient shadow RAM with reset values */
|
||||
for (i = 4; i <= 49; i += 5)
|
||||
@ -924,16 +959,6 @@ static int sta32x_remove(struct snd_soc_codec *codec)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool sta32x_reg_is_volatile(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case STA32X_CONFA ... STA32X_L2ATRT:
|
||||
case STA32X_MPCC1 ... STA32X_FDRC2:
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct snd_soc_codec_driver sta32x_codec = {
|
||||
.probe = sta32x_probe,
|
||||
.remove = sta32x_remove,
|
||||
@ -954,12 +979,16 @@ static const struct regmap_config sta32x_regmap = {
|
||||
.reg_defaults = sta32x_regs,
|
||||
.num_reg_defaults = ARRAY_SIZE(sta32x_regs),
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.volatile_reg = sta32x_reg_is_volatile,
|
||||
.wr_table = &sta32x_write_regs,
|
||||
.rd_table = &sta32x_read_regs,
|
||||
.volatile_table = &sta32x_volatile_regs,
|
||||
};
|
||||
};
|
||||
|
||||
static int sta32x_i2c_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct device *dev = &i2c->dev;
|
||||
struct sta32x_priv *sta32x;
|
||||
int ret, i;
|
||||
|
||||
@ -968,6 +997,8 @@ static int sta32x_i2c_probe(struct i2c_client *i2c,
|
||||
if (!sta32x)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&sta32x->coeff_lock);
|
||||
sta32x->pdata = dev_get_platdata(dev);
|
||||
/* regulators */
|
||||
for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
|
||||
sta32x->supplies[i].supply = sta32x_supply_names[i];
|
||||
@ -982,15 +1013,15 @@ static int sta32x_i2c_probe(struct i2c_client *i2c,
|
||||
sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
|
||||
if (IS_ERR(sta32x->regmap)) {
|
||||
ret = PTR_ERR(sta32x->regmap);
|
||||
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
|
||||
dev_err(dev, "Failed to init regmap: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
i2c_set_clientdata(i2c, sta32x);
|
||||
|
||||
ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1);
|
||||
if (ret != 0)
|
||||
dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
|
||||
ret = snd_soc_register_codec(dev, &sta32x_codec, &sta32x_dai, 1);
|
||||
if (ret < 0)
|
||||
dev_err(dev, "Failed to register codec (%d)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user