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[ARM] S3C: Add SDHCI (HSMMC) channel 1 device definition
Add device definition and support code for the Samsung HSMMC channel 1 device. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -55,6 +55,7 @@ void __init s3c6410_map_io(void)
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/* initialise device information early */
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s3c6410_default_sdhci0();
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s3c6410_default_sdhci1();
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}
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void __init s3c6410_init_clocks(int xtal)
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@ -154,3 +154,9 @@ config S3C_DEV_HSMMC
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depends on PLAT_S3C
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help
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Compile in platform device definitions for HSMMC code
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config S3C_DEV_HSMMC1
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bool
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depends on PLAT_S3C
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help
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Compile in platform device definitions for HSMMC channel 1
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@ -21,3 +21,4 @@ obj-y += gpio-config.o
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# devices
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obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
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obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
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68
arch/arm/plat-s3c/dev-hsmmc1.c
Normal file
68
arch/arm/plat-s3c/dev-hsmmc1.c
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@ -0,0 +1,68 @@
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/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
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*
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* Copyright (c) 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C series device definition for hsmmc device 1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mmc/host.h>
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#include <mach/map.h>
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#include <plat/sdhci.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#define S3C_SZ_HSMMC (0x1000)
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static struct resource s3c_hsmmc1_resource[] = {
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[0] = {
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.start = S3C_PA_HSMMC1,
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.end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_HSMMC1,
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.end = IRQ_HSMMC1,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
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struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
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.max_width = 4,
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.host_caps = (MMC_CAP_4_BIT_DATA |
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MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
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};
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struct platform_device s3c_device_hsmmc1 = {
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.name = "s3c-sdhci",
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.id = 1,
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.num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
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.resource = s3c_hsmmc1_resource,
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.dev = {
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.dma_mask = &s3c_device_hsmmc1_dmamask,
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.coherent_dma_mask = 0xffffffffUL,
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.platform_data = &s3c_hsmmc1_def_platdata,
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},
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};
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void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
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{
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struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
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set->max_width = pd->max_width;
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if (pd->cfg_gpio)
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set->cfg_gpio = pd->cfg_gpio;
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if (pd->cfg_card)
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set->cfg_card = pd->cfg_card;
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}
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@ -56,12 +56,14 @@ struct s3c_sdhci_platdata {
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* make the structure itself __initdata.
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*/
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extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
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extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
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/* Default platform data, exported so that per-cpu initialisation can
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* set the correct one when there are more than one cpu type selected.
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*/
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extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platata;
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extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
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extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
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/* Helper function availablity */
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@ -69,6 +71,8 @@ extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platata;
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extern char *s3c6410_hsmmc_clksrcs[4];
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extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
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extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
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extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
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void __iomem *r,
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struct mmc_ios *ios,
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@ -80,8 +84,16 @@ static inline void s3c6410_default_sdhci0(void)
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s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
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s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
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}
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static inline void s3c6410_default_sdhci1(void)
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{
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s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
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s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
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s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
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}
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#else
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static inline void s3c6410_default_sdhci0(void) { }
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static inline void s3c6410_default_sdhci1(void) { }
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#endif /* CONFIG_S3C6410_SETUP_SDHCI */
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#endif /* __PLAT_S3C_SDHCI_H */
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