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Blackfin: allow CONFIG_TICKSOURCE_GPTMR0 with interrupt pipeline
Signed-off-by: Philippe Gerum <rpm@xenomai.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -623,7 +623,6 @@ choice
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config TICKSOURCE_GPTMR0
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bool "Gptimer0 (SCLK domain)"
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select BFIN_GPTIMERS
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depends on !IPIPE
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config TICKSOURCE_CORETMR
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bool "Core timer (CCLK domain)"
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@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void);
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int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
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#ifdef CONFIG_GENERIC_CLOCKEVENTS
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#ifdef CONFIG_TICKSOURCE_CORETMR
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#define IRQ_SYSTMR IRQ_CORETMR
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#define IRQ_PRIOTMR IRQ_CORETMR
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#else
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@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
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#define ipipe_init_irq_threads() do { } while (0)
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#define ipipe_start_irq_thread(irq, desc) 0
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#ifndef CONFIG_TICKSOURCE_GPTMR0
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#define IRQ_SYSTMR IRQ_CORETMR
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#define IRQ_PRIOTMR IRQ_CORETMR
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#else
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#define IRQ_SYSTMR IRQ_TIMER0
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#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
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#endif
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#define __ipipe_root_tick_p(regs) 1
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@ -1052,35 +1052,34 @@ int __init init_arch_irq(void)
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set_irq_chained_handler(irq, bfin_demux_error_irq);
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break;
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#endif
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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case IRQ_TIMER0:
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set_irq_handler(irq, handle_percpu_irq);
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break;
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#endif
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#ifdef CONFIG_SMP
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case IRQ_SUPPLE_0:
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case IRQ_SUPPLE_1:
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set_irq_handler(irq, handle_percpu_irq);
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break;
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#endif
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default:
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#ifdef CONFIG_IPIPE
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/*
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* We want internal interrupt sources to be
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* masked, because ISRs may trigger interrupts
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* recursively (e.g. DMA), but interrupts are
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* _not_ masked at CPU level. So let's handle
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* most of them as level interrupts, except
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* the timer interrupt which is special.
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*/
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if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
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#ifndef CONFIG_TICKSOURCE_CORETMR
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case IRQ_TIMER0:
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set_irq_handler(irq, handle_simple_irq);
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else
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set_irq_handler(irq, handle_level_irq);
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#else /* !CONFIG_IPIPE */
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set_irq_handler(irq, handle_simple_irq);
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#endif /* !CONFIG_IPIPE */
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break;
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#endif /* !CONFIG_TICKSOURCE_CORETMR */
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case IRQ_CORETMR:
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set_irq_handler(irq, handle_simple_irq);
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break;
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default:
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set_irq_handler(irq, handle_level_irq);
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break;
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#else /* !CONFIG_IPIPE */
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#ifdef CONFIG_TICKSOURCE_GPTMR0
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case IRQ_TIMER0:
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set_irq_handler(irq, handle_percpu_irq);
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break;
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#endif /* CONFIG_TICKSOURCE_GPTMR0 */
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default:
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set_irq_handler(irq, handle_simple_irq);
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break;
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#endif /* !CONFIG_IPIPE */
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}
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}
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@ -1224,15 +1223,14 @@ __attribute__((l1_text))
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asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
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{
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struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
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struct ipipe_domain *this_domain = ipipe_current_domain;
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struct ipipe_domain *this_domain = __ipipe_current_domain;
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struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
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struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
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int irq, s;
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if (likely(vec == EVT_IVTMR_P)) {
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if (likely(vec == EVT_IVTMR_P))
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irq = IRQ_CORETMR;
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} else {
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else {
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#if defined(SIC_ISR0) || defined(SICA_ISR0)
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unsigned long sic_status[3];
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@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
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break;
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}
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#endif
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irq = ivg->irqno;
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}
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if (irq == IRQ_SYSTMR) {
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#ifndef CONFIG_GENERIC_CLOCKEVENTS
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#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
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bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
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#endif
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/* This is basically what we need from the register frame. */
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