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RDMA/nes: Add wide_ppm_offset parm for switch compatibility
We have observed unstable link with a new BNT switch. Add wide_ppm_offset parameter to allow the user to control the clock ppm offset on the CX4 interface for better compatibility. Default is 100ppm, setting it to 1 will increase it to 300ppm. Change default SerDes1 reference clock to external source. Signed-off-by: Chien Tung <chien.tin.tung@intel.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Chien Tung
Roland Dreier
parent
1b9493248c
commit
a4849fc157
@ -46,6 +46,10 @@ static unsigned int nes_lro_max_aggr = NES_LRO_MAX_AGGR;
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module_param(nes_lro_max_aggr, uint, 0444);
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MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation");
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static int wide_ppm_offset;
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module_param(wide_ppm_offset, int, 0644);
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MODULE_PARM_DESC(wide_ppm_offset, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
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static u32 crit_err_count;
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u32 int_mod_timer_init;
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u32 int_mod_cq_depth_256;
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@ -546,8 +550,11 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
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msleep(1);
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}
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if (int_cnt > 1) {
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u32 sds;
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spin_lock_irqsave(&nesadapter->phy_lock, flags);
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
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sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
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sds |= 0x00000040;
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
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mh_detected++;
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reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
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reset_value |= 0x0000003d;
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@ -736,43 +743,48 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
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{
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int i;
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u32 u32temp;
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u32 serdes_common_control;
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u32 sds;
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if (hw_rev != NE020_REV) {
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/* init serdes 0 */
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if (wide_ppm_offset && (nesadapter->phy_type[0] == NES_PHY_TYPE_CX4))
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA);
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else
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
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if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
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serdes_common_control = nes_read_indexed(nesdev,
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NES_IDX_ETH_SERDES_COMMON_CONTROL0);
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serdes_common_control |= 0x000000100;
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nes_write_indexed(nesdev,
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NES_IDX_ETH_SERDES_COMMON_CONTROL0,
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serdes_common_control);
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} else if (!OneG_Mode) {
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sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
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sds |= 0x00000100;
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds);
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}
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if (!OneG_Mode)
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
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if (port_count < 2)
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return 0;
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/* init serdes 1 */
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switch (nesadapter->phy_type[1]) {
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case NES_PHY_TYPE_ARGUS:
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
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break;
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case NES_PHY_TYPE_CX4:
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sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
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sds &= 0xFFFFFFBF;
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
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if (wide_ppm_offset)
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
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else
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
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break;
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case NES_PHY_TYPE_PUMA_1G:
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sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
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sds |= 0x000000100;
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
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}
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if (((port_count > 1) &&
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(nesadapter->phy_type[0] != NES_PHY_TYPE_PUMA_1G)) ||
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((port_count > 2) &&
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(nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G))) {
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/* init serdes 1 */
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if (nesadapter->phy_type[0] == NES_PHY_TYPE_ARGUS) {
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
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}
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
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if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
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serdes_common_control = nes_read_indexed(nesdev,
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NES_IDX_ETH_SERDES_COMMON_CONTROL1);
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serdes_common_control |= 0x000000100;
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nes_write_indexed(nesdev,
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NES_IDX_ETH_SERDES_COMMON_CONTROL1,
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serdes_common_control);
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} else if (!OneG_Mode) {
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
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}
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}
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if (!OneG_Mode)
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
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} else {
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/* init serdes 0 */
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
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@ -2315,6 +2327,7 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
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u16 temp_phy_data;
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u32 pcs_val = 0x0f0f0000;
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u32 pcs_mask = 0x0f1f0000;
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u32 cdr_ctrl;
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spin_lock_irqsave(&nesadapter->phy_lock, flags);
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if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
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@ -2466,6 +2479,17 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
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}
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if (phy_data & 0x0004) {
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if (wide_ppm_offset &&
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(nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
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(nesadapter->hw_rev != NE020_REV)) {
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cdr_ctrl = nes_read_indexed(nesdev,
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NES_IDX_ETH_SERDES_CDR_CONTROL0 +
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mac_index * 0x200);
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nes_write_indexed(nesdev,
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NES_IDX_ETH_SERDES_CDR_CONTROL0 +
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mac_index * 0x200,
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cdr_ctrl | 0x000F0000);
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}
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nesadapter->mac_link_down[mac_index] = 0;
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list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
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nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
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@ -2480,6 +2504,17 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
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}
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}
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} else {
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if (wide_ppm_offset &&
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(nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
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(nesadapter->hw_rev != NE020_REV)) {
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cdr_ctrl = nes_read_indexed(nesdev,
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NES_IDX_ETH_SERDES_CDR_CONTROL0 +
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mac_index * 0x200);
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nes_write_indexed(nesdev,
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NES_IDX_ETH_SERDES_CDR_CONTROL0 +
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mac_index * 0x200,
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cdr_ctrl & 0xFFF0FFFF);
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}
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nesadapter->mac_link_down[mac_index] = 1;
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list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
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nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
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@ -35,6 +35,7 @@
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#include <linux/inet_lro.h>
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#define NES_PHY_TYPE_CX4 1
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#define NES_PHY_TYPE_1G 2
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#define NES_PHY_TYPE_IRIS 3
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#define NES_PHY_TYPE_ARGUS 4
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