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OMAP clock, powerdomain, clockdomain, and hwmod fixes intended for the
early v3.4-rc series. Also contains an HSMMC integration refinement of an earlier hardware bug workaround. ARM: OMAP3: clock data: fill in some missing clockdomains ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch() ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status ARM: OMAP2+: hwmod: Restore sysc after a reset ARM: OMAP: clock: fix race in disable all clocks ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks ARM: OMAP3xxx: HSMMC: avoid erratum workaround when transceiver is attached ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPfWEKAAoJEMePsQ0LvSpLGqIP/1Mvc3O7+Gs97E8BBR7RVkPC Uo4aM6NMwkCBozC9XLooS12FFCC1k97aLh7IeEhN5qZ8U/FqkF6qIdMTLzJpSsnD nuL1JLZGAdd+OtxgbVhjd/3cmK2H94K5XozZrKbC2/fypjDRjh40yk6hIH0zvZU6 +OX6r0kRW9HX6gC2+cAPJzKWaSgVimh6KQxRsevL8xbyPm183/vx2U0E1bicsHrY rSXcQTo0AanDHNX4bSG3lMXiv+hVxYRpzlhJ1ToPN/fRokWXJjp3oycRYVL4A6KE 8MvvSORhf6yVekB+LOESIEmFNisGl/2zuAPFnZBnHzcpvNTvDB57uSPtUeQjXsUK 6MBgW5okGUU9tihP7m8tmP6kbo0tPdZRtBiJP0KDBflLRFAOgrcWiRQL+8jjus0v ktHt6h3P71D8MoYN74T6x2/0NP49FXA3RVxuKDoaT3nXXkR7IvVNVXPh15zRTPFe liTrn0U1Bu34HvpAuR8WRO5W0VgT2DTPQNk7WtZkYlyS1WXLAunDW9+Bv1JHS1MH zeBZf6SNE1kVLWdNkFaYK0pAXHw8epwsUKeI9ZNIX3y9qdamzvafzeKQUjewPbLm 26KOzr3cuwIb7No7sh3fSpJV/Y8YFPCb9MvvzMg5yhfYf2SL4xYrudhSPcCw9gEy 2pCChl33o4AvxjkUEXjZ =41FI -----END PGP SIGNATURE----- Merge tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes From Paul Walmsley: OMAP clock, powerdomain, clockdomain, and hwmod fixes intended for the early v3.4-rc series. Also contains an HSMMC integration refinement of an earlier hardware bug workaround. * tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending: ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status ARM: OMAP2+: hwmod: Restore sysc after a reset ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules ARM: OMAP3: clock data: fill in some missing clockdomains ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch() ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases ARM: OMAP: clock: fix race in disable all clocks ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks ARM: OMAP3xxx: HSMMC: avoid erratum workaround when transceiver is attached ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data
This commit is contained in:
commit
a8f5b6e5ef
@ -747,7 +747,7 @@ static struct clk dpll4_m3_ck = {
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.parent = &dpll4_ck,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
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.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
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.clksel_mask = OMAP3630_CLKSEL_TV_MASK,
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.clksel = dpll4_clksel,
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.clkdm_name = "dpll4_clkdm",
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.recalc = &omap2_clksel_recalc,
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@ -832,7 +832,7 @@ static struct clk dpll4_m4_ck = {
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.parent = &dpll4_ck,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
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.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
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.clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
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.clksel = dpll4_clksel,
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.clkdm_name = "dpll4_clkdm",
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.recalc = &omap2_clksel_recalc,
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@ -859,7 +859,7 @@ static struct clk dpll4_m5_ck = {
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.parent = &dpll4_ck,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
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.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
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.clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
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.clksel = dpll4_clksel,
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.clkdm_name = "dpll4_clkdm",
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.set_rate = &omap2_clksel_set_rate,
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@ -886,7 +886,7 @@ static struct clk dpll4_m6_ck = {
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.parent = &dpll4_ck,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
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.clksel_mask = OMAP3630_DIV_DPLL4_MASK,
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.clksel = dpll4_clksel,
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.clkdm_name = "dpll4_clkdm",
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.recalc = &omap2_clksel_recalc,
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@ -1394,6 +1394,7 @@ static struct clk cpefuse_fck = {
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.name = "cpefuse_fck",
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.ops = &clkops_omap2_dflt,
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.parent = &sys_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
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.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
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.recalc = &followparent_recalc,
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@ -1403,6 +1404,7 @@ static struct clk ts_fck = {
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.name = "ts_fck",
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.ops = &clkops_omap2_dflt,
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.parent = &omap_32k_fck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
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.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
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.recalc = &followparent_recalc,
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@ -1412,6 +1414,7 @@ static struct clk usbtll_fck = {
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.name = "usbtll_fck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &dpll5_m2_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
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.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
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.recalc = &followparent_recalc,
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@ -1617,6 +1620,7 @@ static struct clk fshostusb_fck = {
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.name = "fshostusb_fck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &core_48m_fck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
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.recalc = &followparent_recalc,
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@ -2043,6 +2047,7 @@ static struct clk omapctrl_ick = {
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
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.flags = ENABLE_ON_INIT,
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.clkdm_name = "core_l4_clkdm",
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.recalc = &followparent_recalc,
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};
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@ -2094,6 +2099,7 @@ static struct clk usb_l4_ick = {
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.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
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.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
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.clksel = usb_l4_clksel,
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.clkdm_name = "core_l4_clkdm",
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.recalc = &omap2_clksel_recalc,
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};
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@ -3467,8 +3473,8 @@ static struct omap_clk omap3xxx_clks[] = {
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CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
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CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
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CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
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CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
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CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
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CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX),
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CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
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CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
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CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
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CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
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@ -957,8 +957,8 @@ static struct dpll_data dpll_usb_dd = {
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.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
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.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
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.idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
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.mult_mask = OMAP4430_DPLL_MULT_MASK,
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.div1_mask = OMAP4430_DPLL_DIV_MASK,
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.mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
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.div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
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.enable_mask = OMAP4430_DPLL_EN_MASK,
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.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
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.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
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@ -978,6 +978,7 @@ static struct clk dpll_usb_ck = {
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.recalc = &omap3_dpll_recalc,
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.round_rate = &omap2_dpll_round_rate,
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.set_rate = &omap3_noncore_dpll_set_rate,
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.clkdm_name = "l3_init_clkdm",
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};
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static struct clk dpll_usb_clkdcoldo_ck = {
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@ -390,7 +390,7 @@ static struct clockdomain emu_sys_44xx_clkdm = {
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.cm_inst = OMAP4430_PRM_EMU_CM_INST,
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.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
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};
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static struct clockdomain l3_dma_44xx_clkdm = {
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@ -506,6 +506,13 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
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if (oh->dev_attr != NULL) {
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mmc_dev_attr = oh->dev_attr;
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mmc_data->controller_flags = mmc_dev_attr->flags;
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/*
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* erratum 2.1.1.128 doesn't apply if board has
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* a transceiver is attached
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*/
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if (hsmmcinfo->transceiver)
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mmc_data->controller_flags &=
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~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
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}
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pdev = platform_device_alloc(name, ctrl_nr - 1);
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@ -1479,6 +1479,11 @@ static int _reset(struct omap_hwmod *oh)
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ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
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if (oh->class->sysc) {
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_update_sysc_cache(oh);
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_enable_sysc(oh);
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}
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return ret;
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}
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@ -1788,20 +1793,9 @@ static int _setup(struct omap_hwmod *oh, void *data)
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return 0;
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}
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if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
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if (!(oh->flags & HWMOD_INIT_NO_RESET))
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_reset(oh);
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/*
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* OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
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* The _enable() function should be split to
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* avoid the rewrite of the OCP_SYSCONFIG register.
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*/
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if (oh->class->sysc) {
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_update_sysc_cache(oh);
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_enable_sysc(oh);
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}
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}
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postsetup_state = oh->_postsetup_state;
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if (postsetup_state == _HWMOD_STATE_UNKNOWN)
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postsetup_state = _HWMOD_STATE_ENABLED;
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@ -1909,20 +1903,10 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
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*/
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int omap_hwmod_softreset(struct omap_hwmod *oh)
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{
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u32 v;
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int ret;
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if (!oh || !(oh->_sysc_cache))
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if (!oh)
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return -EINVAL;
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v = oh->_sysc_cache;
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ret = _set_softreset(oh, &v);
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if (ret)
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goto error;
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_write_sysconfig(v, oh);
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error:
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return ret;
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return _ocp_softreset(oh);
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}
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/**
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@ -2465,26 +2449,28 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
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* @oh: struct omap_hwmod *
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*
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* Sets the module OCP socket ENAWAKEUP bit to allow the module to
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* send wakeups to the PRCM. Eventually this should sets PRCM wakeup
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* registers to cause the PRCM to receive wakeup events from the
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* module. Does not set any wakeup routing registers beyond this
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* point - if the module is to wake up any other module or subsystem,
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* that must be set separately. Called by omap_device code. Returns
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* -EINVAL on error or 0 upon success.
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* send wakeups to the PRCM, and enable I/O ring wakeup events for
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* this IP block if it has dynamic mux entries. Eventually this
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* should set PRCM wakeup registers to cause the PRCM to receive
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* wakeup events from the module. Does not set any wakeup routing
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* registers beyond this point - if the module is to wake up any other
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* module or subsystem, that must be set separately. Called by
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* omap_device code. Returns -EINVAL on error or 0 upon success.
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*/
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int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
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{
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unsigned long flags;
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u32 v;
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if (!oh->class->sysc ||
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!(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
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return -EINVAL;
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spin_lock_irqsave(&oh->_lock, flags);
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v = oh->_sysc_cache;
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_enable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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if (oh->class->sysc &&
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(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
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v = oh->_sysc_cache;
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_enable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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}
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_set_idle_ioring_wakeup(oh, true);
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spin_unlock_irqrestore(&oh->_lock, flags);
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@ -2496,26 +2482,28 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
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* @oh: struct omap_hwmod *
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*
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* Clears the module OCP socket ENAWAKEUP bit to prevent the module
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* from sending wakeups to the PRCM. Eventually this should clear
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* PRCM wakeup registers to cause the PRCM to ignore wakeup events
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* from the module. Does not set any wakeup routing registers beyond
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* this point - if the module is to wake up any other module or
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* subsystem, that must be set separately. Called by omap_device
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* code. Returns -EINVAL on error or 0 upon success.
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* from sending wakeups to the PRCM, and disable I/O ring wakeup
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* events for this IP block if it has dynamic mux entries. Eventually
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* this should clear PRCM wakeup registers to cause the PRCM to ignore
|
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* wakeup events from the module. Does not set any wakeup routing
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* registers beyond this point - if the module is to wake up any other
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* module or subsystem, that must be set separately. Called by
|
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* omap_device code. Returns -EINVAL on error or 0 upon success.
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*/
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int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
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{
|
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unsigned long flags;
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u32 v;
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if (!oh->class->sysc ||
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!(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
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return -EINVAL;
|
||||
|
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spin_lock_irqsave(&oh->_lock, flags);
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v = oh->_sysc_cache;
|
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_disable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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|
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if (oh->class->sysc &&
|
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(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
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v = oh->_sysc_cache;
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_disable_wakeup(oh, &v);
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_write_sysconfig(v, oh);
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}
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|
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_set_idle_ioring_wakeup(oh, false);
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spin_unlock_irqrestore(&oh->_lock, flags);
|
||||
|
||||
|
@ -2996,6 +2996,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
|
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&omap44xx_l4_abe__mcbsp1_dma,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
|
||||
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
||||
{ .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
|
||||
.name = "mcbsp1",
|
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.class = &omap44xx_mcbsp_hwmod_class,
|
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@ -3012,6 +3017,8 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
|
||||
.opt_clks = mcbsp1_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
|
||||
};
|
||||
|
||||
/* mcbsp2 */
|
||||
@ -3071,6 +3078,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
|
||||
&omap44xx_l4_abe__mcbsp2_dma,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
|
||||
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
||||
{ .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
|
||||
.name = "mcbsp2",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
@ -3087,6 +3099,8 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
|
||||
.opt_clks = mcbsp2_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
|
||||
};
|
||||
|
||||
/* mcbsp3 */
|
||||
@ -3146,6 +3160,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
|
||||
&omap44xx_l4_abe__mcbsp3_dma,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
|
||||
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
||||
{ .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
|
||||
.name = "mcbsp3",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
@ -3162,6 +3181,8 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
|
||||
.opt_clks = mcbsp3_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
|
||||
};
|
||||
|
||||
/* mcbsp4 */
|
||||
@ -3200,6 +3221,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
|
||||
&omap44xx_l4_per__mcbsp4,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
|
||||
{ .role = "pad_fck", .clk = "pad_clks_ck" },
|
||||
{ .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
|
||||
.name = "mcbsp4",
|
||||
.class = &omap44xx_mcbsp_hwmod_class,
|
||||
@ -3216,6 +3242,8 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
|
||||
.opt_clks = mcbsp4_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -972,7 +972,13 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
|
||||
|
||||
int pwrdm_state_switch(struct powerdomain *pwrdm)
|
||||
{
|
||||
return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
|
||||
int ret;
|
||||
|
||||
ret = pwrdm_wait_transition(pwrdm);
|
||||
if (!ret)
|
||||
ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
|
||||
|
@ -441,6 +441,8 @@ static int __init clk_disable_unused(void)
|
||||
return 0;
|
||||
|
||||
pr_info("clock: disabling unused clocks to save power\n");
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
list_for_each_entry(ck, &clocks, node) {
|
||||
if (ck->ops == &clkops_null)
|
||||
continue;
|
||||
@ -448,10 +450,9 @@ static int __init clk_disable_unused(void)
|
||||
if (ck->usecount > 0 || !ck->enable_reg)
|
||||
continue;
|
||||
|
||||
spin_lock_irqsave(&clockfw_lock, flags);
|
||||
arch_clock->clk_disable_unused(ck);
|
||||
spin_unlock_irqrestore(&clockfw_lock, flags);
|
||||
}
|
||||
spin_unlock_irqrestore(&clockfw_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -47,17 +47,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
|
||||
* with the original PRCM protocol defined for OMAP2420
|
||||
*/
|
||||
#define SYSC_TYPE1_MIDLEMODE_SHIFT 12
|
||||
#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
|
||||
#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
|
||||
#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
|
||||
#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
|
||||
#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
|
||||
#define SYSC_TYPE1_SIDLEMODE_SHIFT 3
|
||||
#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
|
||||
#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
|
||||
#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
|
||||
#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
|
||||
#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
|
||||
#define SYSC_TYPE1_SOFTRESET_SHIFT 1
|
||||
#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
|
||||
#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
|
||||
#define SYSC_TYPE1_AUTOIDLE_SHIFT 0
|
||||
#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
|
||||
#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
|
||||
|
||||
/*
|
||||
* OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
|
||||
|
Loading…
Reference in New Issue
Block a user