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powerpc/powernv: Supports PHB3
The patch intends to initialize PHB3 during system boot stage. The flag "PNV_PHB_MODEL_PHB3" is introduced to differentiate IODA2 compatible PHB3 from other types of PHBs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Gavin Shan
Benjamin Herrenschmidt
parent
a485c70989
commit
aa0c033f99
@ -852,18 +852,19 @@ static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
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return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
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}
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void __init pnv_pci_init_ioda1_phb(struct device_node *np)
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void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
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{
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struct pci_controller *hose;
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static int primary = 1;
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struct pnv_phb *phb;
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unsigned long size, m32map_off, iomap_off, pemap_off;
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const u64 *prop64;
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const u32 *prop32;
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u64 phb_id;
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void *aux;
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long rc;
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pr_info(" Initializing IODA OPAL PHB %s\n", np->full_name);
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pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
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prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
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if (!prop64) {
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@ -890,37 +891,34 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
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hose->last_busno = 0xff;
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hose->private_data = phb;
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phb->opal_id = phb_id;
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phb->type = PNV_PHB_IODA1;
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phb->type = ioda_type;
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/* Detect specific models for error handling */
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if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
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phb->model = PNV_PHB_MODEL_P7IOC;
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else if (of_device_is_compatible(np, "ibm,p8-pciex"))
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phb->model = PNV_PHB_MODEL_PHB3;
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else
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phb->model = PNV_PHB_MODEL_UNKNOWN;
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/* We parse "ranges" now since we need to deduce the register base
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* from the IO base
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*/
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/* Parse 32-bit and IO ranges (if any) */
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pci_process_bridge_OF_ranges(phb->hose, np, primary);
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primary = 0;
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/* Magic formula from Milton */
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/* Get registers */
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phb->regs = of_iomap(np, 0);
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if (phb->regs == NULL)
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pr_err(" Failed to map registers !\n");
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/* XXX This is hack-a-thon. This needs to be changed so that:
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* - we obtain stuff like PE# etc... from device-tree
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* - we properly re-allocate M32 ourselves
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* (the OFW one isn't very good)
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*/
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/* Initialize more IODA stuff */
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phb->ioda.total_pe = 128;
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prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
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if (!prop32)
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phb->ioda.total_pe = 1;
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else
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phb->ioda.total_pe = *prop32;
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phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
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/* OFW Has already off top 64k of M32 space (MSI space) */
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/* FW Has already off top 64k of M32 space (MSI space) */
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phb->ioda.m32_size += 0x10000;
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phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
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@ -930,7 +928,10 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
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phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
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phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
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/* Allocate aux data & arrays */
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/* Allocate aux data & arrays
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*
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* XXX TODO: Don't allocate io segmap on PHB3
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*/
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size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
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m32map_off = size;
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size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
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@ -960,7 +961,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
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hose->mem_resources[2].start = 0;
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hose->mem_resources[2].end = 0;
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#if 0
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#if 0 /* We should really do that ... */
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rc = opal_pci_set_phb_mem_window(opal->phb_id,
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window_type,
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window_num,
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@ -974,16 +975,6 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
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phb->ioda.m32_size, phb->ioda.m32_segsize,
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phb->ioda.io_size, phb->ioda.io_segsize);
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if (phb->regs) {
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pr_devel(" BUID = 0x%016llx\n", in_be64(phb->regs + 0x100));
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pr_devel(" PHB2_CR = 0x%016llx\n", in_be64(phb->regs + 0x160));
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pr_devel(" IO_BAR = 0x%016llx\n", in_be64(phb->regs + 0x170));
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pr_devel(" IO_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x178));
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pr_devel(" IO_SAR = 0x%016llx\n", in_be64(phb->regs + 0x180));
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pr_devel(" M32_BAR = 0x%016llx\n", in_be64(phb->regs + 0x190));
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pr_devel(" M32_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x198));
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pr_devel(" M32_SAR = 0x%016llx\n", in_be64(phb->regs + 0x1a0));
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}
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phb->hose->ops = &pnv_pci_ops;
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/* Setup RID -> PE mapping function */
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@ -1011,9 +1002,20 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
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rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
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if (rc)
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pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
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/*
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* On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset
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* has cleared the RTT which has the same effect
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*/
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if (ioda_type == PNV_PHB_IODA1)
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opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
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}
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void pnv_pci_init_ioda2_phb(struct device_node *np)
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{
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pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2);
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}
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void __init pnv_pci_init_ioda_hub(struct device_node *np)
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{
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struct device_node *phbn;
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@ -1034,6 +1036,6 @@ void __init pnv_pci_init_ioda_hub(struct device_node *np)
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for_each_child_of_node(np, phbn) {
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/* Look for IODA1 PHBs */
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if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
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pnv_pci_init_ioda1_phb(phbn);
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pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1);
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}
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}
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@ -492,7 +492,7 @@ static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
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pnv_pci_dma_fallback_setup(hose, pdev);
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}
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/* Fixup wrong class code in p7ioc root complex */
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/* Fixup wrong class code in p7ioc and p8 root complex */
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static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
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{
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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@ -558,6 +558,10 @@ void __init pnv_pci_init(void)
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if (!found_ioda)
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for_each_compatible_node(np, NULL, "ibm,p5ioc2")
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pnv_pci_init_p5ioc2_hub(np);
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/* Look for ioda2 built-in PHB3's */
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for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
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pnv_pci_init_ioda2_phb(np);
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}
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/* Setup the linkage between OF nodes and PHBs */
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@ -4,9 +4,9 @@
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struct pci_dn;
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enum pnv_phb_type {
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PNV_PHB_P5IOC2,
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PNV_PHB_IODA1,
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PNV_PHB_IODA2,
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PNV_PHB_P5IOC2 = 0,
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PNV_PHB_IODA1 = 1,
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PNV_PHB_IODA2 = 2,
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};
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/* Precise PHB model for error management */
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@ -14,6 +14,7 @@ enum pnv_phb_model {
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PNV_PHB_MODEL_UNKNOWN,
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PNV_PHB_MODEL_P5IOC2,
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PNV_PHB_MODEL_P7IOC,
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PNV_PHB_MODEL_PHB3,
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};
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#define PNV_PCI_DIAG_BUF_SIZE 4096
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@ -148,6 +149,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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u64 dma_offset);
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extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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#endif /* __POWERNV_PCI_H */
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