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drm/amdgpu: Clear vce&uvd ring wptr for SRIOV
MMSCH FW need to get the wptr from 0 after it get the mailbox request from driver, since every time kick the mailbox, mmsch thinks that it is the first time engine start to initialize. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -685,6 +685,11 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
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/* 4, set resp to zero */
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
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WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
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adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
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adev->uvd.ring_enc[0].wptr = 0;
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adev->uvd.ring_enc[0].wptr_old = 0;
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/* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
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WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
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@ -702,7 +707,6 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
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dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
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return -EBUSY;
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}
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WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
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return 0;
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}
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@ -173,6 +173,11 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
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/* 4, set resp to zero */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
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WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
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adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
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adev->vce.ring[0].wptr = 0;
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adev->vce.ring[0].wptr_old = 0;
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/* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
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@ -190,7 +195,6 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
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dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
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return -EBUSY;
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}
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WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
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return 0;
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}
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