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include/asm-m68knommu/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Adrian Bunk <bunk@kernel.org>
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@ -262,7 +262,7 @@ static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned lon
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* tmp = __swab32(*(p++));
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* tmp |= ~0UL >> (32-offset);
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*
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* but this would decrease preformance, so we change the
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* but this would decrease performance, so we change the
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* shift:
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*/
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tmp = *(p++);
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@ -715,7 +715,7 @@ extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
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#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
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#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
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#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
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#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
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#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
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#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
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#define CICR_IEN ((uint)0x00000080) /* Int. enable */
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#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
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@ -68,7 +68,7 @@ static inline void _udelay(unsigned long usecs)
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/*
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* Moved the udelay() function into library code, no longer inlined.
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* I had to change the algorithm because we are overflowing now on
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* the faster ColdFire parts. The code is a little biger, so it makes
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* the faster ColdFire parts. The code is a little bigger, so it makes
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* sense to library it.
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*/
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extern void udelay(unsigned long usecs);
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@ -43,10 +43,10 @@
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#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
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#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
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#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
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#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
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#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
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#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
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#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
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@ -64,22 +64,22 @@
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#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
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#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
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#else
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#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
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#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
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#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
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#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
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#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
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#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */
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#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
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#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
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#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
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#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */
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#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
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#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
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#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
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#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */
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#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
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#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
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#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
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#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */
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#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
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#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
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#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
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#endif /* CONFIG_OLDMASK */
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@ -48,22 +48,22 @@
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#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
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#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
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#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
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#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
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#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
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#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
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#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */
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#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
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#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
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#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
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#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */
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#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
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#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
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#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
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#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */
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#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
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#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
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#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
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#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */
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#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
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#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
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#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
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@ -138,7 +138,7 @@
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#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
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#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
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#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
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#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
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#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
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#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */
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#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
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@ -71,7 +71,7 @@ struct mcf_platform_uart {
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#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
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#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
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#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
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#define MCFUART_UISR 0x14 /* Interrup Status (r) */
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#define MCFUART_UISR 0x14 /* Interrupt Status (r) */
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#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
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#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
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#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
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