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powerpc: Move the testing of CPU_FTR_COHERENT_ICACHE into __flush_icache_range

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In function flush_icache_range(), we use cpu_has_feature() to test
the feature bit of CPU_FTR_COHERENT_ICACHE. But this seems not optimal
for two reasons:
 a) For ppc32, the function __flush_icache_range() already do this
    check with the macro END_FTR_SECTION_IFSET.
 b) Compare with the cpu_has_feature(), the method of using macro
    END_FTR_SECTION_IFSET will not introduce any runtime overhead.

[And while at it, add the missing required isync] -- BenH

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Kevin Hao 2013-08-06 18:23:30 +08:00 committed by Benjamin Herrenschmidt
parent f13c13a005
commit abb29c3bb1
3 changed files with 5 additions and 3 deletions
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3
arch/powerpc/include/asm/cacheflush.h
View File

@ -35,8 +35,7 @@ extern void __flush_disable_L1(void);
extern void __flush_icache_range(unsigned long, unsigned long);
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
__flush_icache_range(start, stop);
__flush_icache_range(start, stop);
}
extern void flush_icache_user_range(struct vm_area_struct *vma,

1
arch/powerpc/kernel/misc_32.S
View File

@ -329,6 +329,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
*/
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
isync
blr /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
li r5,L1_CACHE_BYTES-1

4
arch/powerpc/kernel/misc_64.S
View File

@ -68,7 +68,9 @@ PPC64_CACHES:
*/
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
* Flush the data cache to memory
*