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bnx2x: Change BCM848xx configuration according to IEEE
Change BCM848xx behavior to fit IEEE such that setting 10Mb/100Mb will use force speed, and setting 1Gb/10Gb will use auto-negotiation with the specific speed advertised Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yaniv Rosner
David S. Miller
parent
54c2fb7859
commit
ac4d944910
@ -4354,197 +4354,159 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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}
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
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{
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/* This phy uses the NIG latch mechanism since link
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indication arrives through its LED4 and not via
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its LASI signal, so we get steady signal
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instead of clear on read */
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u16 autoneg_val, an_1000_val, an_10_100_val;
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bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
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1 << NIG_LATCH_BC_ENABLE_MI_INT);
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1 << NIG_LATCH_BC_ENABLE_MI_INT);
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bnx2x_cl45_write(bp, params->port,
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_CTRL, 0x0000);
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_CTRL, 0x0000);
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bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
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if (params->req_line_speed == SPEED_AUTO_NEG) {
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u16 autoneg_val, an_1000_val, an_10_100_val;
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/* set 1000 speed advertisement */
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_1000T_CTRL,
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&an_1000_val);
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if (params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
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an_1000_val |= (1<<8);
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if (params->req_duplex == DUPLEX_FULL)
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an_1000_val |= (1<<9);
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DP(NETIF_MSG_LINK, "Advertising 1G\n");
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} else
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an_1000_val &= ~((1<<8) | (1<<9));
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_1000T_CTRL,
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an_1000_val);
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/* set 100 speed advertisement */
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_AN_ADV,
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&an_10_100_val);
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if (params->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
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PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
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an_10_100_val |= (1<<7);
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if (params->req_duplex == DUPLEX_FULL)
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an_10_100_val |= (1<<8);
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DP(NETIF_MSG_LINK,
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"Advertising 100M\n");
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} else
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an_10_100_val &= ~((1<<7) | (1<<8));
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/* set 10 speed advertisement */
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if (params->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
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an_10_100_val |= (1<<5);
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if (params->req_duplex == DUPLEX_FULL)
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an_10_100_val |= (1<<6);
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DP(NETIF_MSG_LINK, "Advertising 10M\n");
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}
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else
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an_10_100_val &= ~((1<<5) | (1<<6));
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_AN_ADV,
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an_10_100_val);
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_MII_CTRL,
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&autoneg_val);
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/* Disable forced speed */
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autoneg_val &= ~(1<<6|1<<13);
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/* Enable autoneg and restart autoneg
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for legacy speeds */
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autoneg_val |= (1<<9|1<<12);
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_1000T_CTRL,
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&an_1000_val);
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bnx2x_ext_phy_set_pause(params, vars);
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bnx2x_cl45_read(bp, params->port, ext_phy_type,
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ext_phy_addr, MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_AN_ADV,
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&an_10_100_val);
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bnx2x_cl45_read(bp, params->port, ext_phy_type,
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ext_phy_addr, MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_MII_CTRL,
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&autoneg_val);
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/* Disable forced speed */
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autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) |
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(1<<13));
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an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
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if (((params->req_line_speed == SPEED_AUTO_NEG) &&
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(params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
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(params->req_line_speed == SPEED_1000)) {
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an_1000_val |= (1<<8);
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autoneg_val |= (1<<9 | 1<<12);
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if (params->req_duplex == DUPLEX_FULL)
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autoneg_val |= (1<<8);
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else
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autoneg_val &= ~(1<<8);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_MII_CTRL,
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autoneg_val);
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if (params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
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DP(NETIF_MSG_LINK, "Advertising 10G\n");
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/* Restart autoneg for 10G*/
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an_1000_val |= (1<<9);
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DP(NETIF_MSG_LINK, "Advertising 1G\n");
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} else
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an_1000_val &= ~((1<<8) | (1<<9));
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_CTRL, 0x3200);
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}
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} else {
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/* Force speed */
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u16 autoneg_ctrl, pma_ctrl;
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_MII_CTRL,
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&autoneg_ctrl);
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_1000T_CTRL,
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an_1000_val);
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/* Disable autoneg */
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autoneg_ctrl &= ~(1<<12);
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/* set 10 speed advertisement */
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if (((params->req_line_speed == SPEED_AUTO_NEG) &&
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(params->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
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PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
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an_10_100_val |= (1<<7);
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/*
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* Enable autoneg and restart autoneg for
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* legacy speeds
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*/
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autoneg_val |= (1<<9 | 1<<12);
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/* Set 1000 force */
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switch (params->req_line_speed) {
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case SPEED_10000:
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DP(NETIF_MSG_LINK,
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"Unable to set 10G force !\n");
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break;
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case SPEED_1000:
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_CTRL,
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&pma_ctrl);
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autoneg_ctrl &= ~(1<<13);
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autoneg_ctrl |= (1<<6);
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pma_ctrl &= ~(1<<13);
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pma_ctrl |= (1<<6);
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DP(NETIF_MSG_LINK,
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"Setting 1000M force\n");
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_CTRL,
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pma_ctrl);
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break;
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case SPEED_100:
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autoneg_ctrl |= (1<<13);
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autoneg_ctrl &= ~(1<<6);
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DP(NETIF_MSG_LINK,
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"Setting 100M force\n");
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break;
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case SPEED_10:
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autoneg_ctrl &= ~(1<<13);
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autoneg_ctrl &= ~(1<<6);
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DP(NETIF_MSG_LINK,
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"Setting 10M force\n");
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break;
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}
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/* Duplex mode */
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if (params->req_duplex == DUPLEX_FULL) {
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autoneg_ctrl |= (1<<8);
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DP(NETIF_MSG_LINK,
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"Setting full duplex\n");
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} else
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autoneg_ctrl &= ~(1<<8);
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/* Update autoneg ctrl and pma ctrl */
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_MII_CTRL,
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autoneg_ctrl);
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if (params->req_duplex == DUPLEX_FULL)
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an_10_100_val |= (1<<8);
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DP(NETIF_MSG_LINK, "Advertising 100M\n");
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}
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/* set 10 speed advertisement */
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if (((params->req_line_speed == SPEED_AUTO_NEG) &&
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(params->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
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an_10_100_val |= (1<<5);
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autoneg_val |= (1<<9 | 1<<12);
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if (params->req_duplex == DUPLEX_FULL)
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an_10_100_val |= (1<<6);
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DP(NETIF_MSG_LINK, "Advertising 10M\n");
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}
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/* Only 10/100 are allowed to work in FORCE mode */
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if (params->req_line_speed == SPEED_100) {
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autoneg_val |= (1<<13);
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/* Enabled AUTO-MDIX when autoneg is disabled */
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_AUX_CTRL,
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(1<<15 | 1<<9 | 7<<0));
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DP(NETIF_MSG_LINK, "Setting 100M force\n");
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}
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if (params->req_line_speed == SPEED_10) {
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/* Enabled AUTO-MDIX when autoneg is disabled */
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_AUX_CTRL,
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(1<<15 | 1<<9 | 7<<0));
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DP(NETIF_MSG_LINK, "Setting 10M force\n");
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}
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_AN_ADV,
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an_10_100_val);
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if (params->req_duplex == DUPLEX_FULL)
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autoneg_val |= (1<<8);
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_LEGACY_MII_CTRL,
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autoneg_val);
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if (((params->req_line_speed == SPEED_AUTO_NEG) &&
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(params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
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(params->req_line_speed == SPEED_10000)) {
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DP(NETIF_MSG_LINK, "Advertising 10G\n");
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/* Restart autoneg for 10G*/
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_CTRL,
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0x3200);
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} else if (params->req_line_speed != SPEED_10 &&
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params->req_line_speed != SPEED_100)
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bnx2x_cl45_write(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
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1);
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/* Save spirom version */
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bnx2x_save_8481_spirom_version(bp, params->port,
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ext_phy_addr,
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params->shmem_base);
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break;
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}
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
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DP(NETIF_MSG_LINK,
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"XGXS PHY Failure detected 0x%x\n",
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@ -5212,12 +5212,13 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_AN_REG_8073_2_5G 0x8329
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#define MDIO_AN_REG_8727_MISC_CTRL 0x8309
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#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
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#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
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#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
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#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
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#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
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#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
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#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
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#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
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#define IGU_FUNC_BASE 0x0400
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