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microblaze_v8: PVR support, cpuinfo support
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
93139b1cf8
commit
b0c62724a5
209
arch/microblaze/include/asm/pvr.h
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209
arch/microblaze/include/asm/pvr.h
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@ -0,0 +1,209 @@
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/*
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* Support for the MicroBlaze PVR (Processor Version Register)
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*
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* Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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* Copyright (C) 2007 - 2009 PetaLogix
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef _ASM_MICROBLAZE_PVR_H
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#define _ASM_MICROBLAZE_PVR_H
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#define PVR_MSR_BIT 0x400
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struct pvr_s {
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unsigned pvr[16];
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};
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/* The following taken from Xilinx's standalone BSP pvr.h */
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/* Basic PVR mask */
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#define PVR0_PVR_FULL_MASK 0x80000000
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#define PVR0_USE_BARREL_MASK 0x40000000
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#define PVR0_USE_DIV_MASK 0x20000000
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#define PVR0_USE_HW_MUL_MASK 0x10000000
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#define PVR0_USE_FPU_MASK 0x08000000
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#define PVR0_USE_EXC_MASK 0x04000000
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#define PVR0_USE_ICACHE_MASK 0x02000000
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#define PVR0_USE_DCACHE_MASK 0x01000000
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#define PVR0_USE_MMU 0x00800000 /* new */
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#define PVR0_VERSION_MASK 0x0000FF00
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#define PVR0_USER1_MASK 0x000000FF
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/* User 2 PVR mask */
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#define PVR1_USER2_MASK 0xFFFFFFFF
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/* Configuration PVR masks */
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#define PVR2_D_OPB_MASK 0x80000000
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#define PVR2_D_LMB_MASK 0x40000000
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#define PVR2_I_OPB_MASK 0x20000000
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#define PVR2_I_LMB_MASK 0x10000000
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#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
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#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
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#define PVR2_D_PLB_MASK 0x02000000 /* new */
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#define PVR2_I_PLB_MASK 0x01000000 /* new */
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#define PVR2_INTERCONNECT 0x00800000 /* new */
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#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
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#define PVR2_USE_FSL_EXC 0x00040000 /* new */
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#define PVR2_USE_MSR_INSTR 0x00020000
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#define PVR2_USE_PCMP_INSTR 0x00010000
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#define PVR2_AREA_OPTIMISED 0x00008000
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#define PVR2_USE_BARREL_MASK 0x00004000
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#define PVR2_USE_DIV_MASK 0x00002000
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#define PVR2_USE_HW_MUL_MASK 0x00001000
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#define PVR2_USE_FPU_MASK 0x00000800
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#define PVR2_USE_MUL64_MASK 0x00000400
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#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
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#define PVR2_USE_IPLBEXC 0x00000100
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#define PVR2_USE_DPLBEXC 0x00000080
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#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
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#define PVR2_UNALIGNED_EXC_MASK 0x00000020
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#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
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#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
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#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
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#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
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#define PVR2_FPU_EXC_MASK 0x00000001
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/* Debug and exception PVR masks */
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#define PVR3_DEBUG_ENABLED_MASK 0x80000000
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#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
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#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
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#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
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#define PVR3_FSL_LINKS_MASK 0x00000380
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/* ICache config PVR masks */
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#define PVR4_USE_ICACHE_MASK 0x80000000
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#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
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#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
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#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
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#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
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/* DCache config PVR masks */
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#define PVR5_USE_DCACHE_MASK 0x80000000
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#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
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#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
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#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
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#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
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/* ICache base address PVR mask */
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#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
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/* ICache high address PVR mask */
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#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* DCache base address PVR mask */
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#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
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/* DCache high address PVR mask */
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#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* Target family PVR mask */
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#define PVR10_TARGET_FAMILY_MASK 0xFF000000
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/* MMU descrtiption */
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#define PVR11_USE_MMU 0xC0000000
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#define PVR11_MMU_ITLB_SIZE 0x38000000
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#define PVR11_MMU_DTLB_SIZE 0x07000000
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#define PVR11_MMU_TLB_ACCESS 0x00C00000
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#define PVR11_MMU_ZONES 0x003C0000
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/* MSR Reset value PVR mask */
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#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
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/* PVR access macros */
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#define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK)
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#define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK)
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#define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK)
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#define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
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#define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK)
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#define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK)
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#define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
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#define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
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#define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
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#define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK)
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#define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK)
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#define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK)
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#define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK)
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#define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK)
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#define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK)
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#define PVR_INTERRUPT_IS_EDGE(pvr) \
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(pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
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#define PVR_EDGE_IS_POSITIVE(pvr) \
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(pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
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#define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR)
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#define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
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#define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED)
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#define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK)
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#define PVR_OPCODE_0x0_ILLEGAL(pvr) \
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(pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
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#define PVR_UNALIGNED_EXCEPTION(pvr) \
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(pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
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#define PVR_ILL_OPCODE_EXCEPTION(pvr) \
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(pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
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#define PVR_IOPB_BUS_EXCEPTION(pvr) \
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(pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
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#define PVR_DOPB_BUS_EXCEPTION(pvr) \
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(pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
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#define PVR_DIV_ZERO_EXCEPTION(pvr) \
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(pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
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#define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK)
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#define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
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#define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
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#define PVR_NUMBER_OF_PC_BRK(pvr) \
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((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
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#define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \
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((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
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#define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \
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((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
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#define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
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#define PVR_ICACHE_ADDR_TAG_BITS(pvr) \
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((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
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#define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
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#define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
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#define PVR_ICACHE_LINE_LEN(pvr) \
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(1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
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#define PVR_ICACHE_BYTE_SIZE(pvr) \
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(1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
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#define PVR_DCACHE_ADDR_TAG_BITS(pvr) \
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((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
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#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
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#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
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#define PVR_DCACHE_LINE_LEN(pvr) \
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(1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
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#define PVR_DCACHE_BYTE_SIZE(pvr) \
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(1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
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#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
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#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
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#define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
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#define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
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#define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
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#define PVR_MSR_RESET_VALUE(pvr) \
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(pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
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/* mmu */
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#define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30)
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#define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
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#define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
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#define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
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#define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES)
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int cpu_has_pvr(void);
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void get_pvr(struct pvr_s *pvr);
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#endif /* _ASM_MICROBLAZE_PVR_H */
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148
arch/microblaze/kernel/cpu/mb.c
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148
arch/microblaze/kernel/cpu/mb.c
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/*
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* CPU-version specific code
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2006-2009 PetaLogix
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/seq_file.h>
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#include <linux/cpu.h>
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#include <linux/initrd.h>
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#include <linux/bug.h>
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#include <asm/cpuinfo.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/page.h>
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#include <linux/param.h>
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#include <asm/pvr.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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static int show_cpuinfo(struct seq_file *m, void *v)
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{
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int count = 0;
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char *fpga_family = "Unknown";
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char *cpu_ver = "Unknown";
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int i;
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/* Denormalised to get the fpga family string */
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for (i = 0; family_string_lookup[i].s != NULL; i++) {
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if (cpuinfo.fpga_family_code == family_string_lookup[i].k) {
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fpga_family = (char *)family_string_lookup[i].s;
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break;
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}
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}
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/* Denormalised to get the hw version string */
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for (i = 0; cpu_ver_lookup[i].s != NULL; i++) {
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if (cpuinfo.ver_code == cpu_ver_lookup[i].k) {
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cpu_ver = (char *)cpu_ver_lookup[i].s;
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break;
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}
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}
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count = seq_printf(m,
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"CPU-Family: MicroBlaze\n"
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"FPGA-Arch: %s\n"
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"CPU-Ver: %s\n"
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"CPU-MHz: %d.%02d\n"
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"BogoMips: %lu.%02lu\n",
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fpga_family,
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cpu_ver,
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cpuinfo.cpu_clock_freq /
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1000000,
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cpuinfo.cpu_clock_freq %
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1000000,
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loops_per_jiffy / (500000 / HZ),
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(loops_per_jiffy / (5000 / HZ)) % 100);
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count += seq_printf(m,
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"HW:\n Shift:\t\t%s\n"
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" MSR:\t\t%s\n"
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" PCMP:\t\t%s\n"
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" DIV:\t\t%s\n",
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(cpuinfo.use_instr & PVR0_USE_BARREL_MASK) ? "yes" : "no",
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(cpuinfo.use_instr & PVR2_USE_MSR_INSTR) ? "yes" : "no",
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(cpuinfo.use_instr & PVR2_USE_PCMP_INSTR) ? "yes" : "no",
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(cpuinfo.use_instr & PVR0_USE_DIV_MASK) ? "yes" : "no");
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count += seq_printf(m,
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" MMU:\t\t%x\n",
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cpuinfo.mmu);
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count += seq_printf(m,
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" MUL:\t\t%s\n"
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" FPU:\t\t%s\n",
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(cpuinfo.use_mult & PVR2_USE_MUL64_MASK) ? "v2" :
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(cpuinfo.use_mult & PVR0_USE_HW_MUL_MASK) ? "v1" : "no",
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(cpuinfo.use_fpu & PVR2_USE_FPU2_MASK) ? "v2" :
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(cpuinfo.use_fpu & PVR0_USE_FPU_MASK) ? "v1" : "no");
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count += seq_printf(m,
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" Exc:\t\t%s%s%s%s%s%s%s%s\n",
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(cpuinfo.use_exc & PVR2_OPCODE_0x0_ILL_MASK) ? "op0x0 " : "",
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(cpuinfo.use_exc & PVR2_UNALIGNED_EXC_MASK) ? "unal " : "",
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(cpuinfo.use_exc & PVR2_ILL_OPCODE_EXC_MASK) ? "ill " : "",
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(cpuinfo.use_exc & PVR2_IOPB_BUS_EXC_MASK) ? "iopb " : "",
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(cpuinfo.use_exc & PVR2_DOPB_BUS_EXC_MASK) ? "dopb " : "",
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(cpuinfo.use_exc & PVR2_DIV_ZERO_EXC_MASK) ? "zero " : "",
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(cpuinfo.use_exc & PVR2_FPU_EXC_MASK) ? "fpu " : "",
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(cpuinfo.use_exc & PVR2_USE_FSL_EXC) ? "fsl " : "");
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if (cpuinfo.use_icache)
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count += seq_printf(m,
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"Icache:\t\t%ukB\n",
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cpuinfo.icache_size >> 10);
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else
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count += seq_printf(m, "Icache:\t\tno\n");
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if (cpuinfo.use_dcache)
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count += seq_printf(m,
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"Dcache:\t\t%ukB\n",
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cpuinfo.dcache_size >> 10);
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else
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count += seq_printf(m, "Dcache:\t\tno\n");
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count += seq_printf(m,
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"HW-Debug:\t%s\n",
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cpuinfo.hw_debug ? "yes" : "no");
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|
||||
count += seq_printf(m,
|
||||
"PVR-USR1:\t%x\n"
|
||||
"PVR-USR2:\t%x\n",
|
||||
cpuinfo.pvr_user1,
|
||||
cpuinfo.pvr_user2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *c_start(struct seq_file *m, loff_t *pos)
|
||||
{
|
||||
int i = *pos;
|
||||
|
||||
return i < NR_CPUS ? (void *) (i + 1) : NULL;
|
||||
}
|
||||
|
||||
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
||||
{
|
||||
++*pos;
|
||||
return c_start(m, pos);
|
||||
}
|
||||
|
||||
static void c_stop(struct seq_file *m, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
const struct seq_operations cpuinfo_op = {
|
||||
.start = c_start,
|
||||
.next = c_next,
|
||||
.stop = c_stop,
|
||||
.show = show_cpuinfo,
|
||||
};
|
||||
81
arch/microblaze/kernel/cpu/pvr.c
Normal file
81
arch/microblaze/kernel/cpu/pvr.c
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Support for MicroBlaze PVR (processor version register)
|
||||
*
|
||||
* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
|
||||
* Copyright (C) 2007-2009 PetaLogix
|
||||
* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/exceptions.h>
|
||||
#include <asm/pvr.h>
|
||||
|
||||
/*
|
||||
* Until we get an assembler that knows about the pvr registers,
|
||||
* this horrible cruft will have to do.
|
||||
* That hardcoded opcode is mfs r3, rpvrNN
|
||||
*/
|
||||
|
||||
#define get_single_pvr(pvrid, val) \
|
||||
{ \
|
||||
register unsigned tmp __asm__("r3"); \
|
||||
tmp = 0x0; /* Prevent warning about unused */ \
|
||||
__asm__ __volatile__ ( \
|
||||
".byte 0x94,0x60,0xa0, " #pvrid "\n\t" \
|
||||
: "=r" (tmp) : : "memory"); \
|
||||
val = tmp; \
|
||||
}
|
||||
|
||||
/*
|
||||
* Does the CPU support the PVR register?
|
||||
* return value:
|
||||
* 0: no PVR
|
||||
* 1: simple PVR
|
||||
* 2: full PVR
|
||||
*
|
||||
* This must work on all CPU versions, including those before the
|
||||
* PVR was even an option.
|
||||
*/
|
||||
|
||||
int cpu_has_pvr(void)
|
||||
{
|
||||
unsigned flags;
|
||||
unsigned pvr0;
|
||||
|
||||
local_save_flags(flags);
|
||||
|
||||
/* PVR bit in MSR tells us if there is any support */
|
||||
if (!(flags & PVR_MSR_BIT))
|
||||
return 0;
|
||||
|
||||
get_single_pvr(0x00, pvr0);
|
||||
pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
|
||||
|
||||
if (pvr0 & PVR0_PVR_FULL_MASK)
|
||||
return 1;
|
||||
|
||||
/* for partial PVR use static cpuinfo */
|
||||
return 2;
|
||||
}
|
||||
|
||||
void get_pvr(struct pvr_s *p)
|
||||
{
|
||||
get_single_pvr(0, p->pvr[0]);
|
||||
get_single_pvr(1, p->pvr[1]);
|
||||
get_single_pvr(2, p->pvr[2]);
|
||||
get_single_pvr(3, p->pvr[3]);
|
||||
get_single_pvr(4, p->pvr[4]);
|
||||
get_single_pvr(5, p->pvr[5]);
|
||||
get_single_pvr(6, p->pvr[6]);
|
||||
get_single_pvr(7, p->pvr[7]);
|
||||
get_single_pvr(8, p->pvr[8]);
|
||||
get_single_pvr(9, p->pvr[9]);
|
||||
get_single_pvr(10, p->pvr[10]);
|
||||
get_single_pvr(11, p->pvr[11]);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user