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MIPS: TXx9: Add RBTX4939 board support
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/txx9/rbtx4939/Makefile create mode 100644 arch/mips/txx9/rbtx4939/irq.c create mode 100644 arch/mips/txx9/rbtx4939/prom.c create mode 100644 arch/mips/txx9/rbtx4939/setup.c create mode 100644 include/asm-mips/txx9/rbtx4939.h
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
0dcdbe6add
commit
b27311e1ca
@ -567,15 +567,11 @@ cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
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load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
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#
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# Toshiba RBTX4927 board or
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# Toshiba RBTX4937 board
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# Toshiba RBTX49XX boards
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#
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core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
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#
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# Toshiba RBTX4938 board
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#
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core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
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core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
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cflags-y += -Iinclude/asm-mips/mach-generic
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drivers-$(CONFIG_PCI) += arch/mips/pci/
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@ -45,6 +45,14 @@ config TOSHIBA_RBTX4938
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This Toshiba board is based on the TX4938 processor. Say Y here to
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support this machine type
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config TOSHIBA_RBTX4939
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bool "Toshiba RBTX4939 bobard"
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depends on MACH_TX49XX
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select SOC_TX4939
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help
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This Toshiba board is based on the TX4939 processor. Say Y here to
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support this machine type
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config SOC_TX3927
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bool
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select CEVT_TXX9
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@ -371,6 +371,11 @@ static void __init select_board(void)
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case 0x4938:
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txx9_board_vec = &rbtx4938_vec;
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break;
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#endif
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#ifdef CONFIG_TOSHIBA_RBTX4939
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case 0x4939:
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txx9_board_vec = &rbtx4939_vec;
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break;
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#endif
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}
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#endif
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3
arch/mips/txx9/rbtx4939/Makefile
Normal file
3
arch/mips/txx9/rbtx4939/Makefile
Normal file
@ -0,0 +1,3 @@
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obj-y += irq.o setup.o prom.o
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EXTRA_CFLAGS += -Werror
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96
arch/mips/txx9/rbtx4939/irq.c
Normal file
96
arch/mips/txx9/rbtx4939/irq.c
Normal file
@ -0,0 +1,96 @@
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/*
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* Toshiba RBTX4939 interrupt routines
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* Based on linux/arch/mips/txx9/rbtx4938/irq.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/mipsregs.h>
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#include <asm/txx9/rbtx4939.h>
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/*
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* RBTX4939 IOC controller definition
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*/
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static void rbtx4939_ioc_irq_unmask(unsigned int irq)
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{
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int ioc_nr = irq - RBTX4939_IRQ_IOC;
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writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
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}
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static void rbtx4939_ioc_irq_mask(unsigned int irq)
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{
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int ioc_nr = irq - RBTX4939_IRQ_IOC;
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writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
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mmiowb();
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}
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static struct irq_chip rbtx4939_ioc_irq_chip = {
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.name = "IOC",
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.ack = rbtx4939_ioc_irq_mask,
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.mask = rbtx4939_ioc_irq_mask,
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.mask_ack = rbtx4939_ioc_irq_mask,
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.unmask = rbtx4939_ioc_irq_unmask,
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};
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static inline int rbtx4939_ioc_irqroute(void)
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{
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unsigned char istat = readb(rbtx4939_ifac2_addr);
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if (unlikely(istat == 0))
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return -1;
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return RBTX4939_IRQ_IOC + __fls8(istat);
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}
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static int rbtx4939_irq_dispatch(int pending)
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{
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int irq;
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if (pending & CAUSEF_IP7)
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return MIPS_CPU_IRQ_BASE + 7;
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irq = tx4939_irq();
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if (likely(irq >= 0)) {
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/* redirect IOC interrupts */
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switch (irq) {
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case RBTX4939_IRQ_IOCINT:
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irq = rbtx4939_ioc_irqroute();
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break;
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}
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} else if (pending & CAUSEF_IP0)
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irq = MIPS_CPU_IRQ_BASE + 0;
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else if (pending & CAUSEF_IP1)
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irq = MIPS_CPU_IRQ_BASE + 1;
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else
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irq = -1;
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return irq;
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}
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void __init rbtx4939_irq_setup(void)
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{
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int i;
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/* mask all IOC interrupts */
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writeb(0, rbtx4939_ien_addr);
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/* clear SoftInt interrupts */
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writeb(0, rbtx4939_softint_addr);
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txx9_irq_dispatch = rbtx4939_irq_dispatch;
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tx4939_irq_init();
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for (i = RBTX4939_IRQ_IOC;
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i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
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set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
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handle_level_irq);
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set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
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}
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17
arch/mips/txx9/rbtx4939/prom.c
Normal file
17
arch/mips/txx9/rbtx4939/prom.c
Normal file
@ -0,0 +1,17 @@
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/*
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* rbtx4939 specific prom routines
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/rbtx4939.h>
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void __init rbtx4939_prom_init(void)
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{
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tx4939_add_memory_regions();
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txx9_sio_putchar_init(TX4939_SIO_REG(0) & 0xfffffffffULL);
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}
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306
arch/mips/txx9/rbtx4939/setup.c
Normal file
306
arch/mips/txx9/rbtx4939/setup.c
Normal file
@ -0,0 +1,306 @@
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/*
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* Toshiba RBTX4939 setup routines.
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* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/leds.h>
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#include <asm/reboot.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/rbtx4939.h>
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static void rbtx4939_machine_restart(char *command)
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{
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local_irq_disable();
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writeb(1, rbtx4939_reseten_addr);
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writeb(1, rbtx4939_softreset_addr);
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while (1)
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;
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}
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static void __init rbtx4939_time_init(void)
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{
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tx4939_time_init(0);
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}
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static void __init rbtx4939_pci_setup(void)
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{
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#ifdef CONFIG_PCI
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int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
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struct pci_controller *c = &txx9_primary_pcic;
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register_pci_controller(c);
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tx4939_report_pciclk();
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tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
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if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
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(__raw_readq(&tx4939_ccfgptr->pcfg) &
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(TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
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tx4939_report_pci1clk();
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/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
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c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
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register_pci_controller(c);
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tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
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}
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tx4939_setup_pcierr_irq();
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#endif /* CONFIG_PCI */
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}
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static unsigned long long default_ebccr[] __initdata = {
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0x01c0000000007608ULL, /* 64M ROM */
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0x017f000000007049ULL, /* 1M IOC */
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0x0180000000408608ULL, /* ISA */
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0,
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};
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static void __init rbtx4939_ebusc_setup(void)
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{
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int i;
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unsigned int sp;
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/* use user-configured speed */
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sp = TX4939_EBUSC_CR(0) & 0x30;
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default_ebccr[0] |= sp;
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default_ebccr[1] |= sp;
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default_ebccr[2] |= sp;
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/* initialise by myself */
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for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
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if (default_ebccr[i])
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____raw_writeq(default_ebccr[i],
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&tx4939_ebuscptr->cr[i]);
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else
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____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
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& ~8,
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&tx4939_ebuscptr->cr[i]);
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}
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}
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static void __init rbtx4939_update_ioc_pen(void)
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{
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__u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
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__u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
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__u8 pe1 = readb(rbtx4939_pe1_addr);
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__u8 pe2 = readb(rbtx4939_pe2_addr);
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__u8 pe3 = readb(rbtx4939_pe3_addr);
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if (pcfg & TX4939_PCFG_ATA0MODE)
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pe1 |= RBTX4939_PE1_ATA(0);
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else
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pe1 &= ~RBTX4939_PE1_ATA(0);
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if (pcfg & TX4939_PCFG_ATA1MODE) {
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pe1 |= RBTX4939_PE1_ATA(1);
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pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
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} else {
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pe1 &= ~RBTX4939_PE1_ATA(1);
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if (pcfg & TX4939_PCFG_ET0MODE)
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pe1 |= RBTX4939_PE1_RMII(0);
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else
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pe1 &= ~RBTX4939_PE1_RMII(0);
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if (pcfg & TX4939_PCFG_ET1MODE)
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pe1 |= RBTX4939_PE1_RMII(1);
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else
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pe1 &= ~RBTX4939_PE1_RMII(1);
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}
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if (ccfg & TX4939_CCFG_PTSEL)
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pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
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RBTX4939_PE3_VP_S);
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else {
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__u64 vmode = pcfg &
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(TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
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if (vmode == 0)
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pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
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RBTX4939_PE3_VP_S);
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else if (vmode == TX4939_PCFG_VPSMODE) {
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pe3 |= RBTX4939_PE3_VP_P;
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pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
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} else if (vmode == TX4939_PCFG_VSSMODE) {
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pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
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pe3 &= ~RBTX4939_PE3_VP_P;
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} else {
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pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
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pe3 &= ~RBTX4939_PE3_VP_S;
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}
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}
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if (pcfg & TX4939_PCFG_SPIMODE) {
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if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
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pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
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else {
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if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
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pe2 |= RBTX4939_PE2_SIO2;
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pe2 &= ~RBTX4939_PE2_SIO0;
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} else {
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pe2 |= RBTX4939_PE2_SIO0;
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pe2 &= ~RBTX4939_PE2_SIO2;
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}
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}
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if (pcfg & TX4939_PCFG_SIO3MODE)
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pe2 |= RBTX4939_PE2_SIO3;
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else
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pe2 &= ~RBTX4939_PE2_SIO3;
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pe2 &= ~RBTX4939_PE2_SPI;
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} else {
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pe2 |= RBTX4939_PE2_SPI;
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pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
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RBTX4939_PE2_SIO0);
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}
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if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
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pe2 |= RBTX4939_PE2_GPIO;
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else
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pe2 &= ~RBTX4939_PE2_GPIO;
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writeb(pe1, rbtx4939_pe1_addr);
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writeb(pe2, rbtx4939_pe2_addr);
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writeb(pe3, rbtx4939_pe3_addr);
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}
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#define RBTX4939_MAX_7SEGLEDS 8
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#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
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static u8 led_val[RBTX4939_MAX_7SEGLEDS];
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struct rbtx4939_led_data {
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struct led_classdev cdev;
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char name[32];
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unsigned int num;
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};
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/* Use "dot" in 7seg LEDs */
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static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
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enum led_brightness value)
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{
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struct rbtx4939_led_data *led_dat =
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container_of(led_cdev, struct rbtx4939_led_data, cdev);
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unsigned int num = led_dat->num;
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unsigned long flags;
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local_irq_save(flags);
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led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
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writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
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local_irq_restore(flags);
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}
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static int __init rbtx4939_led_probe(struct platform_device *pdev)
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{
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struct rbtx4939_led_data *leds_data;
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int i;
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static char *default_triggers[] __initdata = {
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"heartbeat",
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"ide-disk",
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"nand-disk",
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};
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leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
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GFP_KERNEL);
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if (!leds_data)
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return -ENOMEM;
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for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
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int rc;
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struct rbtx4939_led_data *led_dat = &leds_data[i];
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led_dat->num = i;
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led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
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sprintf(led_dat->name, "rbtx4939:amber:%u", i);
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led_dat->cdev.name = led_dat->name;
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if (i < ARRAY_SIZE(default_triggers))
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led_dat->cdev.default_trigger = default_triggers[i];
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rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
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if (rc < 0)
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return rc;
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led_dat->cdev.brightness_set(&led_dat->cdev, 0);
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}
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return 0;
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}
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static struct platform_driver rbtx4939_led_driver = {
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.driver = {
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.name = "rbtx4939-led",
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.owner = THIS_MODULE,
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},
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};
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static void __init rbtx4939_led_setup(void)
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{
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platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
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platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
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}
|
||||
#else
|
||||
static inline void rbtx4939_led_setup(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init rbtx4939_arch_init(void)
|
||||
{
|
||||
rbtx4939_pci_setup();
|
||||
}
|
||||
|
||||
static void __init rbtx4939_device_init(void)
|
||||
{
|
||||
#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
|
||||
int i, j;
|
||||
unsigned char ethaddr[2][6];
|
||||
for (i = 0; i < 2; i++) {
|
||||
unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
|
||||
if (readb(rbtx4939_bdipsw_addr) & 8) {
|
||||
u16 buf[3];
|
||||
area -= 0x03000000;
|
||||
for (j = 0; j < 3; j++)
|
||||
buf[j] = le16_to_cpup((u16 *)(area + j * 2));
|
||||
memcpy(ethaddr[i], buf, 6);
|
||||
} else
|
||||
memcpy(ethaddr[i], (void *)area, 6);
|
||||
}
|
||||
tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
|
||||
#endif
|
||||
rbtx4939_led_setup();
|
||||
tx4939_wdt_init();
|
||||
}
|
||||
|
||||
static void __init rbtx4939_setup(void)
|
||||
{
|
||||
rbtx4939_ebusc_setup();
|
||||
/* always enable ATA0 */
|
||||
txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
|
||||
rbtx4939_update_ioc_pen();
|
||||
if (txx9_master_clock == 0)
|
||||
txx9_master_clock = 20000000;
|
||||
tx4939_setup();
|
||||
|
||||
_machine_restart = rbtx4939_machine_restart;
|
||||
|
||||
pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
|
||||
readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
|
||||
readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
|
||||
txx9_board_pcibios_setup = tx4927_pcibios_setup;
|
||||
#else
|
||||
set_io_port_base(RBTX4939_ETHER_BASE);
|
||||
#endif
|
||||
|
||||
tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
|
||||
}
|
||||
|
||||
struct txx9_board_vec rbtx4939_vec __initdata = {
|
||||
.system = "Tothiba RBTX4939",
|
||||
.prom_init = rbtx4939_prom_init,
|
||||
.mem_setup = rbtx4939_setup,
|
||||
.irq_setup = rbtx4939_irq_setup,
|
||||
.time_init = rbtx4939_time_init,
|
||||
.device_init = rbtx4939_device_init,
|
||||
.arch_init = rbtx4939_arch_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pci_map_irq = tx4939_pci_map_irq,
|
||||
#endif
|
||||
};
|
||||
@ -8,3 +8,6 @@ BOARD_VEC(rbtx4937_vec)
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938
|
||||
BOARD_VEC(rbtx4938_vec)
|
||||
#endif
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4939
|
||||
BOARD_VEC(rbtx4939_vec)
|
||||
#endif
|
||||
|
||||
133
include/asm-mips/txx9/rbtx4939.h
Normal file
133
include/asm-mips/txx9/rbtx4939.h
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Definitions for RBTX4939
|
||||
*
|
||||
* (C) Copyright TOSHIBA CORPORATION 2005-2006
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __ASM_TXX9_RBTX4939_H
|
||||
#define __ASM_TXX9_RBTX4939_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/tx4939.h>
|
||||
|
||||
/* Address map */
|
||||
#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
|
||||
#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
|
||||
#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
|
||||
#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
|
||||
#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
|
||||
#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
|
||||
#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
|
||||
#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
|
||||
#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
|
||||
#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
|
||||
#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000)
|
||||
#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002)
|
||||
#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004)
|
||||
#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006)
|
||||
#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000)
|
||||
#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000)
|
||||
#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002)
|
||||
#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004)
|
||||
#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006)
|
||||
#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008)
|
||||
#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a)
|
||||
#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000)
|
||||
#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002)
|
||||
#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004)
|
||||
#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006)
|
||||
#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008)
|
||||
#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a)
|
||||
#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
|
||||
#define RBTX4939_7SEG_ADDR(s, ch) \
|
||||
(IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
|
||||
#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
|
||||
#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
|
||||
#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
|
||||
#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
|
||||
|
||||
/* Ethernet port address */
|
||||
#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300)
|
||||
|
||||
/* bits for IEN/IPOL/IFAC */
|
||||
#define RBTX4938_INTB_ISA0 0
|
||||
#define RBTX4938_INTB_ISA11 1
|
||||
#define RBTX4938_INTB_ISA12 2
|
||||
#define RBTX4938_INTB_ISA15 3
|
||||
#define RBTX4938_INTB_I2S 4
|
||||
#define RBTX4938_INTB_SW 5
|
||||
#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0)
|
||||
#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11)
|
||||
#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12)
|
||||
#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15)
|
||||
#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S)
|
||||
#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW)
|
||||
|
||||
/* bits for PE1,PE2,PE3 */
|
||||
#define RBTX4939_PE1_ATA(ch) (0x01 << (ch))
|
||||
#define RBTX4939_PE1_RMII(ch) (0x04 << (ch))
|
||||
#define RBTX4939_PE2_SIO0 0x01
|
||||
#define RBTX4939_PE2_SIO2 0x02
|
||||
#define RBTX4939_PE2_SIO3 0x04
|
||||
#define RBTX4939_PE2_CIR 0x08
|
||||
#define RBTX4939_PE2_SPI 0x10
|
||||
#define RBTX4939_PE2_GPIO 0x20
|
||||
#define RBTX4939_PE3_VP 0x01
|
||||
#define RBTX4939_PE3_VP_P 0x02
|
||||
#define RBTX4939_PE3_VP_S 0x04
|
||||
|
||||
#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
|
||||
#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
|
||||
#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
|
||||
#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
|
||||
#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
|
||||
#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
|
||||
#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR)
|
||||
#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
|
||||
#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
|
||||
#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR)
|
||||
#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR)
|
||||
#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
|
||||
#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
|
||||
#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
|
||||
#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
|
||||
#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
|
||||
#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR)
|
||||
#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR)
|
||||
#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR)
|
||||
#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
|
||||
#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR)
|
||||
#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR)
|
||||
#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR)
|
||||
#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR)
|
||||
#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
|
||||
#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
|
||||
#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
|
||||
#define rbtx4939_7seg_addr(s, ch) \
|
||||
((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
|
||||
#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
|
||||
#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
|
||||
#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
|
||||
|
||||
/*
|
||||
* IRQ mappings
|
||||
*/
|
||||
#define RBTX4939_NR_IRQ_IOC 8
|
||||
|
||||
#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR)
|
||||
#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
|
||||
|
||||
/* IOC (ISA, etc) */
|
||||
#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0))
|
||||
/* Onboard 10M Ether */
|
||||
#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1))
|
||||
|
||||
void rbtx4939_prom_init(void);
|
||||
void rbtx4939_irq_setup(void);
|
||||
|
||||
#endif /* __ASM_TXX9_RBTX4939_H */
|
||||
Loading…
Reference in New Issue
Block a user