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staging: tidspbridge: remove dw_dmmu_base from cfg_hostres struct
We don't need to map iva2 iommu register base address anymore. Signed-off-by: Fernando Guzman Lugo <x0095840@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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parent
f94378f9f9
commit
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@ -833,8 +833,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
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iounmap((void *)host_res->dw_mem_base[3]);
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if (host_res->dw_mem_base[4])
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iounmap((void *)host_res->dw_mem_base[4]);
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if (host_res->dw_dmmu_base)
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iounmap(host_res->dw_dmmu_base);
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if (host_res->dw_per_base)
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iounmap(host_res->dw_per_base);
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if (host_res->dw_per_pm_base)
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@ -848,7 +846,6 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
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host_res->dw_mem_base[2] = (u32) NULL;
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host_res->dw_mem_base[3] = (u32) NULL;
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host_res->dw_mem_base[4] = (u32) NULL;
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host_res->dw_dmmu_base = NULL;
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host_res->dw_sys_ctrl_base = NULL;
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kfree(host_res);
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@ -393,7 +393,6 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
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omap_dspbridge_dev->dev.platform_data;
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struct cfg_hostres *resources = dev_context->resources;
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int status = 0;
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u32 temp;
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if (!dev_context->mbox)
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return 0;
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@ -437,7 +436,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
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omap_mbox_restore_ctx(dev_context->mbox);
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/* Access MMU SYS CONFIG register to generate a short wakeup */
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temp = readl(resources->dw_dmmu_base + 0x10);
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iommu_read_reg(dev_context->dsp_mmu, MMU_SYSCONFIG);
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dev_context->dw_brd_state = BRD_RUNNING;
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} else if (dev_context->dw_brd_state == BRD_RETENTION) {
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@ -68,7 +68,6 @@ struct cfg_hostres {
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void __iomem *dw_per_base;
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u32 dw_per_pm_base;
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u32 dw_core_pm_base;
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void __iomem *dw_dmmu_base;
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void __iomem *dw_sys_ctrl_base;
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};
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@ -743,7 +743,6 @@ static int request_bridge_resources(struct cfg_hostres *res)
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host_res->dw_sys_ctrl_base = ioremap(OMAP_SYSC_BASE, OMAP_SYSC_SIZE);
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dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]);
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dev_dbg(bridge, "dw_mem_base[3] 0x%x\n", host_res->dw_mem_base[3]);
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dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base);
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/* for 24xx base port is not mapping the mamory for DSP
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* internal memory TODO Do a ioremap here */
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@ -797,8 +796,6 @@ int drv_request_bridge_res_dsp(void **phost_resources)
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OMAP_PER_PRM_SIZE);
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host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE,
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OMAP_CORE_PRM_SIZE);
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host_res->dw_dmmu_base = ioremap(OMAP_DMMU_BASE,
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OMAP_DMMU_SIZE);
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dev_dbg(bridge, "dw_mem_base[0] 0x%x\n",
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host_res->dw_mem_base[0]);
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@ -810,7 +807,6 @@ int drv_request_bridge_res_dsp(void **phost_resources)
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host_res->dw_mem_base[3]);
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dev_dbg(bridge, "dw_mem_base[4] 0x%x\n",
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host_res->dw_mem_base[4]);
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dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base);
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shm_size = drv_datap->shm_size;
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if (shm_size >= 0x10000) {
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