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ARM: Device-tree updates

Browse Source 
As usual, this is where the bulk of our changes end up landing each
 merge window.
 
 The individual updates are too many to enumerate, many many platforms
 have seen additions of device descriptions such that they are
 functionally more complete (in fact, this is often the bulk of updates
 we see).
 
 Instead I've mostly focused on highlighting the new platforms below as
 they are introduced. Sometimes the introduction is of mostly a fragment,
 that later gets filled in on later releases, and in some cases it's
 near-complete platform support. The latter is more common for derivative
 platforms that already has similar support in-tree.
 
 Two SoCs are slight outliers from the usual range of additions. Allwinner
 support for F1C100s, a quite old SoC (ARMv5-based) shipping in the
 Lychee Pi Nano platform. At the other end is NXP Layerscape LX2160A,
 a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O aimed at
 infrastructure/networking.
 
 TI updates stick out in the diff stats too, in particular because they
 have moved the description of their L4 on-chip interconnect to devicetree,
 which opens up for removal of even more of their platform-specific
 'hwmod' description tables over the next few releases.
 
 SoCs:
  - Qualcomm QCS404 (4x Cortex-A53)
  - Allwinner T3 (rebranded R40) and f1c100s (armv5)
  - NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
  - NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)
 
 New platforms:
  - Rockchip: Gru Scarlet (RK3188 Tablet)
  - Amlogic: Phicomm N1 (S905D), Libretech S805-AC
  - Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
  - Qualcomm: QCS404 base platform and EVB
  - Qualcomm: Remove of Arrow SD600
  - PXA: First PXA3xx DT board: Raumfeld
  - Aspeed: Facebook Backpack-CMM BMC
  - Renesas iWave G20D-Q7 (RZ/G1N)
  - Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
  - Allwinner Emlid Neutis N5, Mapleboard MP130
  - Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
  - i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
  - VF610: Liebherr's BK4 device, ZII SCU4 AIB board
  - i.MX7D PICO Hobbit baseboard
  - i.MX7ULP EVK board
  - NXP LX2160AQDS and LX2160ARDB boards
 
 Other:
  - Coresight binding updates across the board
  - CPU cooling maps updates across the board
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM Device-tree updates from Olof Johansson:
 "As usual, this is where the bulk of our changes end up landing each
  merge window.

  The individual updates are too many to enumerate, many many platforms
  have seen additions of device descriptions such that they are
  functionally more complete (in fact, this is often the bulk of updates
  we see).

  Instead I've mostly focused on highlighting the new platforms below as
  they are introduced. Sometimes the introduction is of mostly a
  fragment, that later gets filled in on later releases, and in some
  cases it's near-complete platform support. The latter is more common
  for derivative platforms that already has similar support in-tree.

  Two SoCs are slight outliers from the usual range of additions.
  Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping
  in the Lychee Pi Nano platform. At the other end is NXP Layerscape
  LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O
  aimed at infrastructure/networking.

  TI updates stick out in the diff stats too, in particular because they
  have moved the description of their L4 on-chip interconnect to
  devicetree, which opens up for removal of even more of their
  platform-specific 'hwmod' description tables over the next few
  releases.

  SoCs:
   - Qualcomm QCS404 (4x Cortex-A53)
   - Allwinner T3 (rebranded R40) and f1c100s (armv5)
   - NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
   - NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)

  New platforms:
   - Rockchip: Gru Scarlet (RK3188 Tablet)
   - Amlogic: Phicomm N1 (S905D), Libretech S805-AC
   - Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
   - Qualcomm: QCS404 base platform and EVB
   - Qualcomm: Remove of Arrow SD600
   - PXA: First PXA3xx DT board: Raumfeld
   - Aspeed: Facebook Backpack-CMM BMC
   - Renesas iWave G20D-Q7 (RZ/G1N)
   - Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
   - Allwinner Emlid Neutis N5, Mapleboard MP130
   - Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
   - i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
   - VF610: Liebherr's BK4 device, ZII SCU4 AIB board
   - i.MX7D PICO Hobbit baseboard
   - i.MX7ULP EVK board
   - NXP LX2160AQDS and LX2160ARDB boards

  Other:
   - Coresight binding updates across the board
   - CPU cooling maps updates across the board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (648 commits)
  ARM: dts: suniv: Fix improper bindings include patch
  ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards
  arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node
  ARM: dts: suniv: Fix improper bindings include patch
  arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
  arm64: dts: Remove unused properties from FSL QSPI driver nodes
  ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
  ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes
  ARM: dts: Remove unused properties from FSL QSPI driver nodes
  arm64: dts: ti: k3-am654: Enable main domain McSPI0
  arm64: dts: ti: k3-am654: Add McSPI DT nodes
  arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes
  arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
  arm64: dts: ti: k3-am65-main: Add ECAP PWM node
  arm64: dts: ti: k3-am654-base-board: Add I2C nodes
  arm64: dts: ti: am654-base-board: Add pinmux for main uart0
  arm64: dts: ti: k3-am65: Add pinctrl regions
  dt-bindings: pinctrl: k3: Introduce pinmux definitions
  ARM: dts: exynos: Specify I2S assigned clocks in proper node
  ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2
  ...
This commit is contained in:
Linus Torvalds 2018-12-31 17:36:02 -08:00
commit b7badd1d7a
695 changed files with 37343 additions and 11961 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/amlogic,scpi.txt
View File

@ -17,4 +17,11 @@ Required sub-node properties:
- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
memory on Amlogic GXBB SoC.
Sensor bindings for the sensors based on SCPI Message Protocol
--------------------------------------------------------------
SCPI provides an API to access the various sensors on the SoC.
Required properties:
- compatible : should be "amlogic,meson-gxbb-scpi-sensors".
[0] Documentation/devicetree/bindings/arm/arm,scpi.txt

2
Documentation/devicetree/bindings/arm/amlogic.txt
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@ -91,8 +91,10 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- "phicomm,n1" (Meson gxl s905d)
- "amlogic,p241" (Meson gxl s805x)
- "libretech,aml-s805x-ac" (Meson gxl s805x)
- "amlogic,p281" (Meson gxl s905w)
- "oranth,tx3-mini" (Meson gxl s905w)

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Documentation/devicetree/bindings/arm/emtrion.txt Normal file
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@ -0,0 +1,12 @@
Emtrion Devicetree Bindings
===========================
emCON Series:
-------------
Required root node properties
- compatible:
- "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base
- "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM
- "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base

23
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt Normal file
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@ -0,0 +1,23 @@
Freescale i.MX7ULP Power Management Components
----------------------------------------------
The Multi-System Mode Controller (MSMC) is responsible for sequencing
the MCU into and out of all stop and run power modes. Specifically, it
monitors events to trigger transitions between power modes while
controlling the power, clocks, and memories of the MCU to achieve the
power consumption and functionality of that mode.
The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
Standby modes for either Cortex family. Run, Wait, and Stop are the
common terms used for the primary operating modes of Kinetis
microcontrollers.
Required properties:
- compatible: Should be "fsl,imx7ulp-smc1".
- reg: Specifies base physical address and size of the register sets.
Example:
smc1: smc1@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
};

8
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -101,6 +101,10 @@ i.MX7 SabreSD Board
Required root node properties:
- compatible = "fsl,imx7d-sdb", "fsl,imx7d";
i.MX7ULP Evaluation Kit
Required root node properties:
- compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
Generic i.MX boards
-------------------
@ -123,6 +127,10 @@ i.MX6q generic board
Required root node properties:
- compatible = "fsl,imx6q";
i.MX7ULP generic board
Required root node properties:
- compatible = "fsl,imx7ulp";
Freescale Vybrid Platform Device Tree Bindings
----------------------------------------------

20
Documentation/devicetree/bindings/arm/renesas,prr.txt Normal file
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@ -0,0 +1,20 @@
Renesas Product Register
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
allows to retrieve SoC product and revision information. If present, a device
node for this register should be added.
Required properties:
- compatible: Must be one of:
"renesas,prr"
"renesas,bsid"
- reg: Base address and length of the register block.
Examples
--------
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};

240
Documentation/devicetree/bindings/arm/rockchip.txt
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@ -1,240 +0,0 @@
Rockchip platforms device tree bindings
---------------------------------------
- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
Required root node properties:
- compatible = "vamrs,ficus", "rockchip,rk3399";
- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
Required root node properties:
- compatible = "vamrs,rock960", "rockchip,rk3399";
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
- Asus Tinker board
Required root node properties:
- compatible = "asus,rk3288-tinker", "rockchip,rk3288";
- Asus Tinker board S
Required root node properties:
- compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
- Kylin RK3036 board:
Required root node properties:
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
- MarsBoard RK3066 board:
Required root node properties:
- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
- bq Curie 2 tablet:
Required root node properties:
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
- ChipSPARK Rayeager PX2 board:
Required root node properties:
- compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
- Radxa Rock board:
Required root node properties:
- compatible = "radxa,rock", "rockchip,rk3188";
- Radxa Rock2 Square board:
Required root node properties:
- compatible = "radxa,rock2-square", "rockchip,rk3288";
- Rikomagic MK808 v1 board:
Required root node properties:
- compatible = "rikomagic,mk808", "rockchip,rk3066a";
- Firefly Firefly-RK3288 board:
Required root node properties:
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
or
- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
- Firefly Firefly-RK3288 Reload board:
Required root node properties:
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
- Firefly Firefly-RK3399 board:
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
- Firefly roc-rk3328-cc board:
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
- Firefly ROC-RK3399-PC board:
Required root node properties:
- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
- Netxeon R89 board:
Required root node properties:
- compatible = "netxeon,r89", "rockchip,rk3288";
- GeekBuying GeekBox:
Required root node properties:
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
- Google Bob (Asus Chromebook Flip C101PA):
Required root node properties:
compatible = "google,bob-rev13", "google,bob-rev12",
"google,bob-rev11", "google,bob-rev10",
"google,bob-rev9", "google,bob-rev8",
"google,bob-rev7", "google,bob-rev6",
"google,bob-rev5", "google,bob-rev4",
"google,bob", "google,gru", "rockchip,rk3399";
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
"google,veyron", "rockchip,rk3288";
- Google Gru (dev-board):
Required root node properties:
- compatible = "google,gru-rev15", "google,gru-rev14",
"google,gru-rev13", "google,gru-rev12",
"google,gru-rev11", "google,gru-rev10",
"google,gru-rev9", "google,gru-rev8",
"google,gru-rev7", "google,gru-rev6",
"google,gru-rev5", "google,gru-rev4",
"google,gru-rev3", "google,gru-rev2",
"google,gru", "rockchip,rk3399";
- Google Jaq (Haier Chromebook 11 and more):
Required root node properties:
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
"google,veyron-jaq-rev1", "google,veyron-jaq",
"google,veyron", "rockchip,rk3288";
- Google Jerry (Hisense Chromebook C11 and more):
Required root node properties:
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
"google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288";
- Google Kevin (Samsung Chromebook Plus):
Required root node properties:
- compatible = "google,kevin-rev15", "google,kevin-rev14",
"google,kevin-rev13", "google,kevin-rev12",
"google,kevin-rev11", "google,kevin-rev10",
"google,kevin-rev9", "google,kevin-rev8",
"google,kevin-rev7", "google,kevin-rev6",
"google,kevin", "google,gru", "rockchip,rk3399";
- Google Mickey (Asus Chromebit CS10):
Required root node properties:
- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
"google,veyron-mickey-rev0", "google,veyron-mickey",
"google,veyron", "rockchip,rk3288";
- Google Minnie (Asus Chromebook Flip C100P):
Required root node properties:
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
"google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
"google,veyron-minnie-rev0", "google,veyron-minnie",
"google,veyron", "rockchip,rk3288";
- Google Pinky (dev-board):
Required root node properties:
- compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
"google,veyron", "rockchip,rk3288";
- Google Speedy (Asus C201 Chromebook):
Required root node properties:
- compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
- mqmaker MiQi:
Required root node properties:
- compatible = "mqmaker,miqi", "rockchip,rk3288";
- Phytec phyCORE-RK3288: Rapid Development Kit
Required root node properties:
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
- Pine64 Rock64 board:
Required root node properties:
- compatible = "pine64,rock64", "rockchip,rk3328";
- Pine64 RockPro64 board:
Required root node properties:
- compatible = "pine64,rockpro64", "rockchip,rk3399";
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
- Rockchip PX5 Evaluation board:
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
- Rockchip PX30 Evaluation board:
Required root node properties:
- compatible = "rockchip,px30-evb", "rockchip,px30";
- Rockchip RV1108 Evaluation board
Required root node properties:
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
- Rockchip RK3368 evb:
Required root node properties:
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
- Rockchip R88 board:
Required root node properties:
- compatible = "rockchip,r88", "rockchip,rk3368";
- Rockchip RK3228 Evaluation board:
Required root node properties:
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
- Rockchip RK3229 Evaluation board:
- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
- Rockchip RK3288 Fennec board:
Required root node properties:
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
- Rockchip RK3328 evb:
Required root node properties:
- compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
- Rockchip RK3399 Sapphire board standalone:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";

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Documentation/devicetree/bindings/arm/rockchip.yaml Normal file
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@ -0,0 +1,423 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/rockchip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip platforms device tree bindings
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
items:
- const: vamrs,ficus
- const: rockchip,rk3399
- description: 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
items:
- const: vamrs,rock960
- const: rockchip,rk3399
- description: Amarula Vyasa RK3288
items:
- const: amarula,vyasa-rk3288
- const: rockchip,rk3288
- description: Asus Tinker board
items:
- const: asus,rk3288-tinker
- const: rockchip,rk3288
- description: Asus Tinker board S
items:
- const: asus,rk3288-tinker-s
- const: rockchip,rk3288
- description: bq Curie 2 tablet
items:
- const: mundoreader,bq-curie2
- const: rockchip,rk3066a
- description: bq Edison 2 Quad-Core tablet
items:
- const: mundoreader,bq-edison2qc
- const: rockchip,rk3188
- description: ChipSPARK PopMetal-RK3288
items:
- const: chipspark,popmetal-rk3288
- const: rockchip,rk3288
- description: ChipSPARK Rayeager PX2
items:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
- description: Firefly Firefly-RK3288
items:
- enum:
- firefly,firefly-rk3288
- firefly,firefly-rk3288-beta
- const: rockchip,rk3288
- description: Firefly Firefly-RK3288 Reload
items:
- const: firefly,firefly-rk3288-reload
- const: rockchip,rk3288
- description: Firefly Firefly-RK3399
items:
- const: firefly,firefly-rk3399
- const: rockchip,rk3399
- description: Firefly roc-rk3328-cc
items:
- const: firefly,roc-rk3328-cc
- const: rockchip,rk3328
- description: Firefly ROC-RK3399-PC
items:
- const: firefly,roc-rk3399-pc
- const: rockchip,rk3399
- description: GeekBuying GeekBox
items:
- const: geekbuying,geekbox
- const: rockchip,rk3368
- description: Google Bob (Asus Chromebook Flip C101PA)
items:
- const: google,bob-rev13
- const: google,bob-rev12
- const: google,bob-rev11
- const: google,bob-rev10
- const: google,bob-rev9
- const: google,bob-rev8
- const: google,bob-rev7
- const: google,bob-rev6
- const: google,bob-rev5
- const: google,bob-rev4
- const: google,bob
- const: google,gru
- const: rockchip,rk3399
- description: Google Brain (dev-board)
items:
- const: google,veyron-brain-rev0
- const: google,veyron-brain
- const: google,veyron
- const: rockchip,rk3288
- description: Google Gru (dev-board)
items:
- const: google,gru-rev15
- const: google,gru-rev14
- const: google,gru-rev13
- const: google,gru-rev12
- const: google,gru-rev11
- const: google,gru-rev10
- const: google,gru-rev9
- const: google,gru-rev8
- const: google,gru-rev7
- const: google,gru-rev6
- const: google,gru-rev5
- const: google,gru-rev4
- const: google,gru-rev3
- const: google,gru-rev2
- const: google,gru
- const: rockchip,rk3399
- description: Google Jaq (Haier Chromebook 11 and more)
items:
- const: google,veyron-jaq-rev5
- const: google,veyron-jaq-rev4
- const: google,veyron-jaq-rev3
- const: google,veyron-jaq-rev2
- const: google,veyron-jaq-rev1
- const: google,veyron-jaq
- const: google,veyron
- const: rockchip,rk3288
- description: Google Jerry (Hisense Chromebook C11 and more)
items:
- const: google,veyron-jerry-rev7
- const: google,veyron-jerry-rev6
- const: google,veyron-jerry-rev5
- const: google,veyron-jerry-rev4
- const: google,veyron-jerry-rev3
- const: google,veyron-jerry
- const: google,veyron
- const: rockchip,rk3288
- description: Google Kevin (Samsung Chromebook Plus)
items:
- const: google,kevin-rev15
- const: google,kevin-rev14
- const: google,kevin-rev13
- const: google,kevin-rev12
- const: google,kevin-rev11
- const: google,kevin-rev10
- const: google,kevin-rev9
- const: google,kevin-rev8
- const: google,kevin-rev7
- const: google,kevin-rev6
- const: google,kevin
- const: google,gru
- const: rockchip,rk3399
- description: Google Mickey (Asus Chromebit CS10)
items:
- const: google,veyron-mickey-rev8
- const: google,veyron-mickey-rev7
- const: google,veyron-mickey-rev6
- const: google,veyron-mickey-rev5
- const: google,veyron-mickey-rev4
- const: google,veyron-mickey-rev3
- const: google,veyron-mickey-rev2
- const: google,veyron-mickey-rev1
- const: google,veyron-mickey-rev0
- const: google,veyron-mickey
- const: google,veyron
- const: rockchip,rk3288
- description: Google Minnie (Asus Chromebook Flip C100P)
items:
- const: google,veyron-minnie-rev4
- const: google,veyron-minnie-rev3
- const: google,veyron-minnie-rev2
- const: google,veyron-minnie-rev1
- const: google,veyron-minnie-rev0
- const: google,veyron-minnie
- const: google,veyron
- const: rockchip,rk3288
- description: Google Pinky (dev-board)
items:
- const: google,veyron-pinky-rev2
- const: google,veyron-pinky
- const: google,veyron
- const: rockchip,rk3288
- description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10)
items:
- const: google,scarlet-rev15-sku7
- const: google,scarlet-rev15
- const: google,scarlet-rev14-sku7
- const: google,scarlet-rev14
- const: google,scarlet-rev13-sku7
- const: google,scarlet-rev13
- const: google,scarlet-rev12-sku7
- const: google,scarlet-rev12
- const: google,scarlet-rev11-sku7
- const: google,scarlet-rev11
- const: google,scarlet-rev10-sku7
- const: google,scarlet-rev10
- const: google,scarlet-rev9-sku7
- const: google,scarlet-rev9
- const: google,scarlet-rev8-sku7
- const: google,scarlet-rev8
- const: google,scarlet-rev7-sku7
- const: google,scarlet-rev7
- const: google,scarlet-rev6-sku7
- const: google,scarlet-rev6
- const: google,scarlet-rev5-sku7
- const: google,scarlet-rev5
- const: google,scarlet-rev4-sku7
- const: google,scarlet-rev4
- const: google,scarlet-rev3-sku7
- const: google,scarlet-rev3
- const: google,scarlet
- const: google,gru
- const: rockchip,rk3399
- description: Google Scarlet - Innolux display (Acer Chromebook Tab 10)
items:
- const: google,scarlet-rev15-sku6
- const: google,scarlet-rev15
- const: google,scarlet-rev14-sku6
- const: google,scarlet-rev14
- const: google,scarlet-rev13-sku6
- const: google,scarlet-rev13
- const: google,scarlet-rev12-sku6
- const: google,scarlet-rev12
- const: google,scarlet-rev11-sku6
- const: google,scarlet-rev11
- const: google,scarlet-rev10-sku6
- const: google,scarlet-rev10
- const: google,scarlet-rev9-sku6
- const: google,scarlet-rev9
- const: google,scarlet-rev8-sku6
- const: google,scarlet-rev8
- const: google,scarlet-rev7-sku6
- const: google,scarlet-rev7
- const: google,scarlet-rev6-sku6
- const: google,scarlet-rev6
- const: google,scarlet-rev5-sku6
- const: google,scarlet-rev5
- const: google,scarlet-rev4-sku6
- const: google,scarlet-rev4
- const: google,scarlet
- const: google,gru
- const: rockchip,rk3399
- description: Google Speedy (Asus C201 Chromebook)
items:
- const: google,veyron-speedy-rev9
- const: google,veyron-speedy-rev8
- const: google,veyron-speedy-rev7
- const: google,veyron-speedy-rev6
- const: google,veyron-speedy-rev5
- const: google,veyron-speedy-rev4
- const: google,veyron-speedy-rev3
- const: google,veyron-speedy-rev2
- const: google,veyron-speedy
- const: google,veyron
- const: rockchip,rk3288
- description: Haoyu MarsBoard RK3066
items:
- const: haoyu,marsboard-rk3066
- const: rockchip,rk3066a
- description: mqmaker MiQi
items:
- const: mqmaker,miqi
- const: rockchip,rk3288
- description: Netxeon R89 board
items:
- const: netxeon,r89
- const: rockchip,rk3288
- description: Phytec phyCORE-RK3288 Rapid Development Kit
items:
- const: phytec,rk3288-pcm-947
- const: phytec,rk3288-phycore-som
- const: rockchip,rk3288
- description: Pine64 Rock64
items:
- const: pine64,rock64
- const: rockchip,rk3328
- description: Pine64 RockPro64
items:
- const: pine64,rockpro64
- const: rockchip,rk3399
- description: Radxa Rock
items:
- const: radxa,rock
- const: rockchip,rk3188
- description: Radxa Rock2 Square
items:
- const: radxa,rock2-square
- const: rockchip,rk3288
- description: Rikomagic MK808 v1
items:
- const: rikomagic,mk808
- const: rockchip,rk3066a
- description: Rockchip Kylin
items:
- const: rockchip,kylin-rk3036
- const: rockchip,rk3036
- description: Rockchip PX3 Evaluation board
items:
- const: rockchip,px3-evb
- const: rockchip,px3
- const: rockchip,rk3188
- description: Rockchip PX30 Evaluation board
items:
- const: rockchip,px30-evb
- const: rockchip,px30
- description: Rockchip PX5 Evaluation board
items:
- const: rockchip,px5-evb
- const: rockchip,px5
- const: rockchip,rk3368
- description: Rockchip R88
items:
- const: rockchip,r88
- const: rockchip,rk3368
- description: Rockchip RK3228 Evaluation board
items:
- const: rockchip,rk3228-evb
- const: rockchip,rk3228
- description: Rockchip RK3229 Evaluation board
items:
- const: rockchip,rk3229-evb
- const: rockchip,rk3229
- description: Rockchip RK3288 Evaluation board
items:
- enum:
- rockchip,rk3288-evb-act8846
- rockchip,rk3288-evb-rk808
- const: rockchip,rk3288
- description: Rockchip RK3288 Fennec
items:
- const: rockchip,rk3288-fennec
- const: rockchip,rk3288
- description: Rockchip RK3328 Evaluation board
items:
- const: rockchip,rk3328-evb
- const: rockchip,rk3328
- description: Rockchip RK3368 Evaluation board (act8846 pmic)
items:
- const: rockchip,rk3368-evb-act8846
- const: rockchip,rk3368
- description: Rockchip RK3399 Evaluation board
items:
- const: rockchip,rk3399-evb
- const: rockchip,rk3399
- description: Rockchip RK3399 Sapphire standalone
items:
- const: rockchip,rk3399-sapphire
- const: rockchip,rk3399
- description: Rockchip RK3399 Sapphire with Excavator Baseboard
items:
- const: rockchip,rk3399-sapphire-excavator
- const: rockchip,rk3399
- description: Rockchip RV1108 Evaluation board
items:
- const: rockchip,rv1108-evb
- const: rockchip,rv1108
- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
items:
- const: tsd,rk3368-uq7-haikou
- const: rockchip,rk3368
- description: Theobroma Systems RK3399-Q7 with Haikou baseboard
items:
- const: tsd,rk3399-q7-haikou
- const: rockchip,rk3399
- description: Tronsmart Orion R68 Meta
items:
- const: tronsmart,orion-r68-meta
- const: rockchip,rk3368
...

22
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -101,6 +101,10 @@ Boards:
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
compatible = "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"
- iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
compatible = "iwave,g20m", "renesas,r8a7744"
- Kingfisher (SBEV-RCAR-KF-M03)
compatible = "shimafuji,kingfisher"
- Koelsch (RTP0RC7791SEB00010S)
@ -149,21 +153,3 @@ Boards:
compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
allows to retrieve SoC product and revision information. If present, a device
node for this register should be added.
Required properties:
- compatible: Must be "renesas,prr" or "renesas,bsid"
- reg: Base address and length of the register block.
Examples
--------
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};

0
Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt → Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
View File

47
Documentation/devicetree/bindings/arm/socionext/uniphier.txt Normal file
View File

@ -0,0 +1,47 @@
Socionext UniPhier SoC family
-----------------------------
Required properties in the root node:
- compatible: should contain board and SoC compatible strings
SoC and board compatible strings:
(sorted chronologically)
- LD4 SoC: "socionext,uniphier-ld4"
- Reference Board: "socionext,uniphier-ld4-ref"
- Pro4 SoC: "socionext,uniphier-pro4"
- Reference Board: "socionext,uniphier-pro4-ref"
- Ace Board: "socionext,uniphier-pro4-ace"
- Sanji Board: "socionext,uniphier-pro4-sanji"
- sLD8 SoC: "socionext,uniphier-sld8"
- Reference Board: "socionext,uniphier-sld8-ref"
- PXs2 SoC: "socionext,uniphier-pxs2"
- Gentil Board: "socionext,uniphier-pxs2-gentil"
- Vodka Board: "socionext,uniphier-pxs2-vodka"
- LD6b SoC: "socionext,uniphier-ld6b"
- Reference Board: "socionext,uniphier-ld6b-ref"
- LD11 SoC: "socionext,uniphier-ld11"
- Reference Board: "socionext,uniphier-ld11-ref"
- Global Board: "socionext,uniphier-ld11-global"
- LD20 SoC: "socionext,uniphier-ld20"
- Reference Board: "socionext,uniphier-ld20-ref"
- Global Board: "socionext,uniphier-ld20-global"
- PXs3 SoC: "socionext,uniphier-pxs3"
- Reference Board: "socionext,uniphier-pxs3-ref"
Example:
/dts-v1/;
/ {
compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
...
};

3
Documentation/devicetree/bindings/arm/sunxi.txt
View File

@ -14,7 +14,8 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
allwinner-sun8i-r40
allwinner,sun8i-r40
allwinner,sun8i-t3
allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64

3
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
View File

@ -15,6 +15,9 @@ Required properties:
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
Example:

10
Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
View File

@ -11,6 +11,13 @@ Required Properties:
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
- clocks: list of clock phandle, one for each entry clock-names.
- clock-names: should contain the following:
* "xtal" : the platform xtal
* "mpeg-clk" : the main clock controller mother clock (aka clk81)
* "ext-32k-0" : external 32kHz reference #0 if any (optional)
* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
- #clock-cells: should be 1.
@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:

5
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
View File

@ -9,6 +9,9 @@ Required Properties:
"amlogic,gxbb-clkc" for GXBB SoC,
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
- #clock-cells: should be 1.
@ -31,6 +34,8 @@ sysctrl: system-controller@0 {
clkc: clock-controller {
#clock-cells = <1>;
compatible = "amlogic,gxbb-clkc";
clocks = <&xtal>;
clock-names = "xtal";
};
};

5
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
View File

@ -11,6 +11,7 @@ Required properties:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ allwinner,sun8i-h3-mali
+ allwinner,sun50i-a64-mali
+ allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
@ -73,6 +74,10 @@ to specify one more vendor-specific compatible, among:
Required properties:
* resets: phandle to the reset line for the GPU
- allwinner,sun50i-a64-mali
Required properties:
* resets: phandle to the reset line for the GPU
- allwinner,sun50i-h5-mali
Required properties:
* resets: phandle to the reset line for the GPU

6
Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
View File

@ -140,6 +140,10 @@ VADC_GND_REF and VADC_VDD_VADC.
Example:
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <linux/irq.h>
/* ... */
/* VADC node */
pmic_vadc: vadc@3100 {
compatible = "qcom,spmi-vadc";
@ -151,7 +155,7 @@ Example:
io-channel-ranges;
/* Channel node */
usb_id_nopull {
adc-chan@VADC_LR_MUX10_USB_ID {
reg = <VADC_LR_MUX10_USB_ID>;
qcom,decimation = <512>;
qcom,ratiometric;

2
Documentation/devicetree/bindings/media/cedrus.txt
View File

@ -33,7 +33,7 @@ reserved-memory {
ranges;
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
cma_pool: cma@4a000000 {
cma_pool: default-pool {
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x4a000000 0x6000000>;

4
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt → Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
View File

@ -10,6 +10,8 @@ Properties:
and chosen using the ramcode board selector. If omitted, only one
set of tables can be present and said tables will be used
irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
Child device nodes describe the memory settings for different configurations and clock rates.
@ -20,6 +22,8 @@ Example:
#size-cells = < 0 >;
compatible = "nvidia,tegra20-emc";
reg = <0x7000f4000 0x200>;
interrupts = <0 78 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
}

1
Documentation/devicetree/bindings/net/dwmac-sun8i.txt
View File

@ -10,6 +10,7 @@ Required properties:
"allwinner,sun8i-r40-gmac"
"allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac"
"allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac"
- reg: address and length of the register for the device.
- interrupts: interrupt for the device
- interrupt-names: must be "macirq"

7
Documentation/devicetree/bindings/pci/layerscape-pci.txt
View File

@ -13,11 +13,12 @@ information.
Required properties:
- compatible: should contain the platform identifier such as:
"fsl,ls1021a-pcie", "snps,dw-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
"fsl,ls1021a-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
"fsl,ls2088a-pcie"
"fsl,ls1088a-pcie"
"fsl,ls1046a-pcie"
"fsl,ls1043a-pcie"
"fsl,ls1012a-pcie"
- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
@ -35,7 +36,7 @@ Required properties:
Example:
pcie@3400000 {
compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
compatible = "fsl,ls1021a-pcie";
reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";

3
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt
View File

@ -2,7 +2,8 @@ Broadcom VCHIQ firmware services
Required properties:
- compatible: Should be "brcm,bcm2835-vchiq"
- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise
"brcm,bcm2836-vchiq".
- reg: Physical base address and length of the doorbell register pair
- interrupts: The interrupt number
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

3
Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt
View File

@ -15,7 +15,8 @@ Required properties:
- compatible:
Array of strings.
One of:
- "nvidia,tegra186-bpmp-thermal".
- "nvidia,tegra186-bpmp-thermal"
- "nvidia,tegra194-bpmp-thermal"
- #thermal-sensor-cells: Cell for sensor index.
Single-cell integer.
Must be <1>.

11
Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
View File

@ -4,12 +4,19 @@ Required properties:
- compatible : should be "amlogic,meson6-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupt of the first timer
- interrupts : The four interrupts, one for each timer event
- clocks : phandles to the pclk (system clock) and XTAL clocks
- clock-names : must contain "pclk" and "xtal"
Example:
timer@c1109940 {
compatible = "amlogic,meson6-timer";
reg = <0xc1109940 0x14>;
interrupts = <0 10 1>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clk81>;
clock-names = "xtal", "pclk";
};

4
Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt
View File

@ -5,9 +5,13 @@ Required properties:
- reg : Address and length of the register set of timer controller.
- interrupts : Should be the interrupt number.
Optional properties:
- clocks : Should contain a single entry describing the clock input.
Example:
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
clocks = <&coreclk 2>;
};

1
Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt
View File

@ -2,6 +2,7 @@ Rockchip rk timer
Required properties:
- compatible: should be:
"rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108
"rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036
"rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066
"rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188

8
Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
View File

@ -59,6 +59,14 @@ For Tegra210:
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
- power-domains: A list of PM domain specifiers that reference each power-domain
used by the xHCI controller. This list must comprise of a specifier for the
XUSBA and XUSBC power-domains. See ../power/power_domain.txt and
../arm/tegra/nvidia,tegra20-pmc.txt for details.
- power-domain-names: A list of names that represent each of the specifiers in
the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which
represent the power-domains XUSBA and XUSBC, respectively. See
../power/power_domain.txt for details.
Optional properties:
--------------------

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -114,6 +114,7 @@ edt Emerging Display Technologies
eeti eGalax_eMPIA Technology Inc
elan Elan Microelectronic Corp.
embest Shenzhen Embest Technology Co., Ltd.
emlid Emlid, Ltd.
emmicro EM Microelectronic
emtrion emtrion GmbH
endless Endless Mobile, Inc.
@ -298,6 +299,7 @@ panasonic Panasonic Corporation
parade Parade Technologies Inc.
pericom Pericom Technology Inc.
pervasive Pervasive Displays, Inc.
phicomm PHICOMM Co., Ltd.
phytec PHYTEC Messtechnik GmbH
picochip Picochip Ltd
pine64 Pine64

9
MAINTAINERS
View File

@ -2225,6 +2225,7 @@ S: Supported
F: Documentation/devicetree/bindings/arm/ti/k3.txt
F: arch/arm64/boot/dts/ti/Makefile
F: arch/arm64/boot/dts/ti/k3-*
F: include/dt-bindings/pinctrl/k3.h
ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE
M: Santosh Shilimkar <ssantosh@kernel.org>
@ -2268,6 +2269,7 @@ M: Masahiro Yamada <yamada.masahiro@socionext.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
S: Maintained
F: Documentation/devicetree/bindings/arm/socionext/uniphier.txt
F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
F: arch/arm/boot/dts/uniphier*
@ -12582,6 +12584,13 @@ L: linux-arm-msm@vger.kernel.org
S: Maintained
F: drivers/iommu/qcom_iommu.c
QUALCOMM TSENS THERMAL DRIVER
M: Amit Kucheria <amit.kucheria@linaro.org>
L: linux-pm@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: drivers/thermal/qcom/
QUALCOMM VENUS VIDEO ACCELERATOR DRIVER
M: Stanimir Varbanov <stanimir.varbanov@linaro.org>
L: linux-media@vger.kernel.org

26
arch/arm/boot/dts/Makefile
View File

@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac68u.dtb \
bcm4708-buffalo-wzr-1750dhp.dtb \
bcm4708-linksys-ea6300-v1.dtb \
bcm4708-linksys-ea6500-v2.dtb \
bcm4708-luxul-xap-1510.dtb \
bcm4708-luxul-xwc-1000.dtb \
bcm4708-netgear-r6250.dtb \
@ -396,6 +397,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-emcon-avari.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
@ -460,6 +462,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-dms-ba16.dtb \
imx6q-emcon-avari.dtb \
imx6q-evi.dtb \
imx6q-gk802.dtb \
imx6q-gw51xx.dtb \
@ -557,6 +560,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-liteboard.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
@ -569,18 +573,23 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-nitrogen7.dtb \
imx7d-pico-hobbit.dtb \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
ls1021a-twr.dtb
dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-bk4.dtb \
vf610-colibri-eval-v3.dtb \
vf610m4-colibri.dtb \
vf610-cosmic.dtb \
@ -589,6 +598,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
vf610-zii-dev-rev-c.dtb \
vf610-zii-scu4-aib.dtb \
vf610-zii-ssmb-spu3.dtb
dtb-$(CONFIG_ARCH_MXS) += \
imx23-evk.dtb \
@ -778,12 +788,18 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_PXA) += \
pxa300-raumfeld-connector.dtb \
pxa300-raumfeld-controller.dtb \
pxa300-raumfeld-speaker-l.dtb \
pxa300-raumfeld-speaker-m.dtb \
pxa300-raumfeld-speaker-one.dtb \
pxa300-raumfeld-speaker-s.dtb
dtb-$(CONFIG_ARCH_OXNAS) += \
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
qcom-apq8064-sony-xperia-yuga.dtb \
@ -829,6 +845,8 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7744-iwg20d-q7.dtb \
r8a7744-iwg20d-q7-dbcm-ca.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
@ -854,6 +872,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
@ -1043,6 +1062,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-bananapi-m2-plus-v1.2.dtb \
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-mapleboard-mp130.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
@ -1060,12 +1080,15 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
@ -1212,6 +1235,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-opp-lanyang.dtb \

2
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -419,6 +419,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-boneblue.dts
View File

@ -515,7 +515,7 @@
&rtc {
system-power-controller;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-cm-t335.dts
View File

@ -393,7 +393,7 @@ status = "okay";
&epwmss0 {
status = "okay";
ecap0: ecap@48300100 {
ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;

4
arch/arm/boot/dts/am335x-evm.dts
View File

@ -519,7 +519,7 @@
&epwmss0 {
status = "okay";
ecap0: ecap@48300100 {
ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
@ -797,6 +797,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

4
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -540,7 +540,7 @@
&epwmss2 {
status = "okay";
ecap2: ecap@48304100 {
ecap2: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
@ -738,6 +738,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-osd3358-sm-red.dts
View File

@ -456,6 +456,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

4
arch/arm/boot/dts/am335x-shc.dts
View File

@ -138,7 +138,7 @@
&epwmss1 {
status = "okay";
ehrpwm1: pwm@48302200 {
ehrpwm1: pwm@200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
@ -205,7 +205,7 @@
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
cpsw_emac0: slave@4a100200 {
cpsw_emac0: slave@200 {
phy-mode = "mii";
phy-handle = <&ethernetphy0>;
};

110
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -334,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@ -407,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@ -477,7 +477,7 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
@ -539,86 +539,140 @@
};
&prcm {
l4_per_cm: l4_per_cm@0 {
per_cm: per-cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x200>;
reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x200>;
ranges = <0 0x0 0x400>;
l4_per_clkctrl: clk@14 {
l4ls_clkctrl: l4ls-clkctrl@38 {
compatible = "ti,clkctrl";
reg = <0x14 0x13c>;
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
#clock-cells = <2>;
};
l3s_clkctrl: l3s-clkctrl@1c {
compatible = "ti,clkctrl";
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
#clock-cells = <2>;
};
l3_clkctrl: l3-clkctrl@24 {
compatible = "ti,clkctrl";
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
#clock-cells = <2>;
};
l4hs_clkctrl: l4hs-clkctrl@120 {
compatible = "ti,clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
compatible = "ti,clkctrl";
reg = <0xe8 0x4>;
#clock-cells = <2>;
};
cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x18>;
#clock-cells = <2>;
};
lcdc_clkctrl: lcdc-clkctrl@18 {
compatible = "ti,clkctrl";
reg = <0x18 0x4>;
#clock-cells = <2>;
};
clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
compatible = "ti,clkctrl";
reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
l4_wkup_cm: l4_wkup_cm@400 {
wkup_cm: wkup-cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
l4_wkup_clkctrl: clk@4 {
l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x4 0xd4>;
reg = <0x0 0x10>, <0xb4 0x24>;
#clock-cells = <2>;
};
l3_aon_clkctrl: l3-aon-clkctrl@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x4>;
#clock-cells = <2>;
};
l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
compatible = "ti,clkctrl";
reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@600 {
mpu_cm: mpu-cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
mpu_clkctrl: clk@4 {
mpu_clkctrl: mpu-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@800 {
l4_rtc_cm: l4-rtc-cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
l4_rtc_clkctrl: clk@0 {
l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@900 {
gfx_l3_cm: gfx-l3-cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
gfx_l3_clkctrl: clk@4 {
gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
l4_cefuse_cm: l4_cefuse_cm@a00 {
l4_cefuse_cm: l4-cefuse-cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
l4_cefuse_clkctrl: clk@20 {
l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
reg = <0x0 0x24>;
#clock-cells = <2>;
};
};

2132
arch/arm/boot/dts/am33xx-l4.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

623
arch/arm/boot/dts/am33xx.dtsi
View File

@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
@ -166,87 +167,23 @@
ranges;
ti,hwmods = "l3_main";
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am3-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@210000 {
compatible = "ti,am3-scm", "simple-bus";
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
scm_conf: scm_conf@0 {
compatible = "syscon", "simple-bus";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x800>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <32>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
};
l4_per: interconnect@48000000 {
};
l4_fw: interconnect@47c00000 {
};
l4_fast: interconnect@4a000000 {
};
l4_mpuss: interconnect@4b140000 {
};
intc: interrupt-controller@48200000 {
@ -297,166 +234,6 @@
interrupt-names = "edma3_tcerrint";
};
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x44e07000 0x1000>;
interrupts = <96>;
};
gpio1: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4804c000 0x1000>;
interrupts = <98>;
};
gpio2: gpio@481ac000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x481ac000 0x1000>;
interrupts = <32>;
};
gpio3: gpio@481ae000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x481ae000 0x1000>;
interrupts = <62>;
};
uart0: serial@44e09000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26 0>, <&edma 27 0>;
dma-names = "tx", "rx";
};
uart1: serial@48022000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28 0>, <&edma 29 0>;
dma-names = "tx", "rx";
};
uart2: serial@48024000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30 0>, <&edma 31 0>;
dma-names = "tx", "rx";
};
uart3: serial@481a6000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
interrupts = <44>;
status = "disabled";
};
uart4: serial@481a8000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
interrupts = <45>;
status = "disabled";
};
uart5: serial@481aa000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
interrupts = <46>;
status = "disabled";
};
i2c0: i2c@44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
reg = <0x44e0b000 0x1000>;
interrupts = <70>;
status = "disabled";
};
i2c1: i2c@4802a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
reg = <0x4802a000 0x1000>;
interrupts = <71>;
status = "disabled";
};
i2c2: i2c@4819c000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
reg = <0x4819c000 0x1000>;
interrupts = <30>;
status = "disabled";
};
mmc1: mmc@48060000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
ti,needs-special-hs-handling;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
interrupts = <64>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
mmc2: mmc@481d8000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2 0
&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <28>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
mmc3: mmc@47810000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc3";
@ -466,157 +243,6 @@
status = "disabled";
};
hwspinlock: spinlock@480ca000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
wdt2: wdt@44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
reg = <0x44e35000 0x1000>;
interrupts = <91>;
};
dcan0: can@481cc000 {
compatible = "ti,am3352-d_can";
ti,hwmods = "d_can0";
reg = <0x481cc000 0x2000>;
clocks = <&dcan0_fck>;
clock-names = "fck";
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <52>;
status = "disabled";
};
dcan1: can@481d0000 {
compatible = "ti,am3352-d_can";
ti,hwmods = "d_can1";
reg = <0x481d0000 0x2000>;
clocks = <&dcan1_fck>;
clock-names = "fck";
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <55>;
status = "disabled";
};
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
};
timer1: timer@44e31000 {
compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
compatible = "ti,am335x-timer";
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
compatible = "ti,am335x-timer";
reg = <0x48042000 0x400>;
interrupts = <69>;
ti,hwmods = "timer3";
};
timer4: timer@48044000 {
compatible = "ti,am335x-timer";
reg = <0x48044000 0x400>;
interrupts = <92>;
ti,hwmods = "timer4";
ti,timer-pwm;
};
timer5: timer@48046000 {
compatible = "ti,am335x-timer";
reg = <0x48046000 0x400>;
interrupts = <93>;
ti,hwmods = "timer5";
ti,timer-pwm;
};
timer6: timer@48048000 {
compatible = "ti,am335x-timer";
reg = <0x48048000 0x400>;
interrupts = <94>;
ti,hwmods = "timer6";
ti,timer-pwm;
};
timer7: timer@4804a000 {
compatible = "ti,am335x-timer";
reg = <0x4804a000 0x400>;
interrupts = <95>;
ti,hwmods = "timer7";
ti,timer-pwm;
};
rtc: rtc@44e3e000 {
compatible = "ti,am3352-rtc", "ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
spi0: spi@48030000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48030000 0x400>;
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
dmas = <&edma 16 0
&edma 17 0
&edma 18 0
&edma 19 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
spi1: spi@481a0000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x481a0000 0x400>;
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
dmas = <&edma 42 0
&edma 43 0
&edma 44 0
&edma 45 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
usb: usb@47400000 {
compatible = "ti,am33xx-usb";
reg = <0x47400000 0x1000>;
@ -747,163 +373,6 @@
};
};
epwmss0: epwmss@48300000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */
ecap0: ecap@48300100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <31>;
interrupt-names = "ecap0";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss1: epwmss@48302000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48302000 0x10>;
ti,hwmods = "epwmss1";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
0x48302180 0x48302180 0x80 /* EQEP */
0x48302200 0x48302200 0x80>; /* EHRPWM */
ecap1: ecap@48302100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <47>;
interrupt-names = "ecap1";
status = "disabled";
};
ehrpwm1: pwm@48302200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss2: epwmss@48304000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48304000 0x10>;
ti,hwmods = "epwmss2";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48304100 0x48304100 0x80 /* ECAP */
0x48304180 0x48304180 0x80 /* EQEP */
0x48304200 0x48304200 0x80>; /* EHRPWM */
ecap2: ecap@48304100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <61>;
interrupt-names = "ecap2";
status = "disabled";
};
ehrpwm2: pwm@48304200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
mac: ethernet@4a100000 {
compatible = "ti,am335x-cpsw","ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x4a100000 0x800
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@4a101000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x4a101000 0x100>;
status = "disabled";
};
cpsw_emac0: slave@4a100200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@4a100300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@44e10650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg= <0x44e10650 0x4>;
reg-names = "gmii-sel";
};
};
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
@ -924,40 +393,6 @@
};
};
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
interrupts = <4>;
ti,hwmods = "elm";
status = "disabled";
};
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
};
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
};
am335x_adc: adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
@ -1005,42 +440,8 @@
<&edma 5 0>;
dma-names = "tx", "rx";
};
mcasp0: mcasp@48038000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp0";
reg = <0x48038000 0x2000>,
<0x46000000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
<0x46400000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <82>, <83>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};
rng: rng@48310000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48310000 0x2000>;
interrupts = <111>;
};
};
};
#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"

4
arch/arm/boot/dts/am3517-evm.dts
View File

@ -20,6 +20,10 @@
display0 = &lcd0;
};
chosen {
stdout-path = &uart3;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */

876
arch/arm/boot/dts/am4372.dtsi
View File

@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>
@ -159,12 +160,7 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am4372-wkup-m3";
reg = <0x100000 0x4000>,
@ -173,75 +169,10 @@
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@210000 {
compatible = "ti,am4-scm", "simple-bus";
reg = <0x210000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x4000>;
am43xx_pinmux: pinmux@800 {
compatible = "ti,am437-padconf",
"pinctrl-single";
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x44>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <64>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
};
l4_per: interconnect@48000000 {
};
l4_fast: interconnect@4a000000 {
};
emif: emif@4c000000 {
@ -297,333 +228,6 @@
interrupt-names = "edma3_tcerrint";
};
uart0: serial@44e09000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x44e09000 0x2000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
};
uart1: serial@48022000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x48022000 0x2000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
status = "disabled";
};
uart2: serial@48024000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x48024000 0x2000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
status = "disabled";
};
uart3: serial@481a6000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481a6000 0x2000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
status = "disabled";
};
uart4: serial@481a8000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481a8000 0x2000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
status = "disabled";
};
uart5: serial@481aa000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481aa000 0x2000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
status = "disabled";
};
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
};
timer1: timer@44e31000 {
compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48042000 0x400>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
status = "disabled";
};
timer4: timer@48044000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48044000 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer4";
status = "disabled";
};
timer5: timer@48046000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48046000 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer5";
status = "disabled";
};
timer6: timer@48048000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48048000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer6";
status = "disabled";
};
timer7: timer@4804a000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x4804a000 0x400>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer7";
status = "disabled";
};
timer8: timer@481c1000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x481c1000 0x400>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
status = "disabled";
};
timer9: timer@4833d000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x4833d000 0x400>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
status = "disabled";
};
timer10: timer@4833f000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x4833f000 0x400>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
status = "disabled";
};
timer11: timer@48341000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48341000 0x400>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
status = "disabled";
};
counter32k: counter@44e86000 {
compatible = "ti,am4372-counter32k","ti,omap-counter32k";
reg = <0x44e86000 0x40>;
ti,hwmods = "counter_32k";
};
rtc: rtc@44e3e000 {
compatible = "ti,am4372-rtc", "ti,am3352-rtc",
"ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "rtc";
clocks = <&clk_32768_ck>;
clock-names = "int-clk";
system-power-controller;
status = "disabled";
};
wdt: wdt@44e35000 {
compatible = "ti,am4372-wdt","ti,omap3-wdt";
reg = <0x44e35000 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
};
gpio0: gpio@44e07000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x44e07000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio1";
status = "disabled";
};
gpio1: gpio@4804c000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x4804c000 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio2";
status = "disabled";
};
gpio2: gpio@481ac000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x481ac000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio3";
status = "disabled";
};
gpio3: gpio@481ae000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x481ae000 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio4";
status = "disabled";
};
gpio4: gpio@48320000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x48320000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio5";
status = "disabled";
};
gpio5: gpio@48322000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x48322000 0x1000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio6";
status = "disabled";
};
hwspinlock: spinlock@480ca000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
i2c0: i2c@44e0b000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x44e0b000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "i2c1";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@4802a000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x4802a000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "i2c2";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@4819c000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x4819c000 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "i2c3";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@48030000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x48030000 0x400>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi0";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmc1: mmc@48060000 {
compatible = "ti,omap4-hsmmc";
reg = <0x48060000 0x1000>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&edma 24 0>,
<&edma 25 0>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mmc2: mmc@481d8000 {
compatible = "ti,omap4-hsmmc";
reg = <0x481d8000 0x1000>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2 0>,
<&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mmc3: mmc@47810000 {
compatible = "ti,omap4-hsmmc";
reg = <0x47810000 0x1000>;
@ -633,282 +237,6 @@
status = "disabled";
};
spi1: spi@481a0000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x481a0000 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi1";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@481a2000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x481a2000 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi2";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@481a4000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x481a4000 0x400>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi3";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@48345000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x48345000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi4";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mac: ethernet@4a100000 {
compatible = "ti,am4372-cpsw","ti,cpsw";
reg = <0x4a100000 0x800
0x4a101200 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
<&dpll_clksel_mac_clk>;
clock-names = "fck", "cpts", "50mclk";
assigned-clocks = <&dpll_clksel_mac_clk>;
assigned-clock-rates = <50000000>;
status = "disabled";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
ranges;
syscon = <&scm_conf>;
davinci_mdio: mdio@4a101000 {
compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x4a101000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
status = "disabled";
};
cpsw_emac0: slave@4a100200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@4a100300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@44e10650 {
compatible = "ti,am43xx-cpsw-phy-sel";
reg= <0x44e10650 0x4>;
reg-names = "gmii-sel";
};
};
epwmss0: epwmss@48300000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss0";
status = "disabled";
ecap0: ecap@48300100 {
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss1: epwmss@48302000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48302000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss1";
status = "disabled";
ecap1: ecap@48302100 {
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm1: pwm@48302200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss2: epwmss@48304000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48304000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss2";
status = "disabled";
ecap2: ecap@48304100 {
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm2: pwm@48304200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss3: epwmss@48306000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48306000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss3";
status = "disabled";
ehrpwm3: pwm@48306200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48306200 0x80>;
clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss4: epwmss@48308000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48308000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss4";
status = "disabled";
ehrpwm4: pwm@48308200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48308200 0x80>;
clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss5: epwmss@4830a000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x4830a000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss5";
status = "disabled";
ehrpwm5: pwm@4830a200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4830a200 0x80>;
clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
ti,hwmods = "adc_tsc";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adc_tsc_fck>;
clock-names = "fck";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
};
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
@ -938,53 +266,6 @@
dma-names = "tx", "rx";
};
rng: rng@48310000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48310000 0x2000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
};
mcasp0: mcasp@48038000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp0";
reg = <0x48038000 0x2000>,
<0x46000000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
<0x46400000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "elm";
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
@ -1005,102 +286,6 @@
status = "disabled";
};
ocp2scp0: ocp2scp@483a8000 {
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp0";
usb2_phy1: phy@483a8000 {
compatible = "ti,am437x-usb2";
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
<&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
ocp2scp1: ocp2scp@483e8000 {
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp1";
usb2_phy2: phy@483e8000 {
compatible = "ti,am437x-usb2";
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
<&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
dwc3_1: omap_dwc3@48380000 {
compatible = "ti,am437x-dwc3";
ti,hwmods = "usb_otg_ss0";
reg = <0x48380000 0x10000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <1>;
ranges;
usb1: usb@48390000 {
compatible = "synopsys,dwc3";
reg = <0x48390000 0x10000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "otg";
status = "disabled";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
dwc3_2: omap_dwc3@483c0000 {
compatible = "ti,am437x-dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x483c0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <1>;
ranges;
usb2: usb@483d0000 {
compatible = "synopsys,dwc3";
reg = <0x483d0000 0x10000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "otg";
status = "disabled";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
@ -1114,16 +299,6 @@
status = "disabled";
};
hdq: hdq@48347000 {
compatible = "ti,am4372-hdq";
reg = <0x48347000 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&func_12m_clk>;
clock-names = "fck";
ti,hwmods = "hdq1w";
status = "disabled";
};
dss: dss@4832a000 {
compatible = "ti,omap3-dss";
reg = <0x4832a000 0x200>;
@ -1173,45 +348,8 @@
pool;
};
};
dcan0: can@481cc000 {
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
ti,hwmods = "d_can0";
clocks = <&dcan0_fck>;
clock-names = "fck";
reg = <0x481cc000 0x2000>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
dcan1: can@481d0000 {
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
ti,hwmods = "d_can1";
clocks = <&dcan1_fck>;
clock-names = "fck";
reg = <0x481d0000 0x2000>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
vpfe0: vpfe@48326000 {
compatible = "ti,am437x-vpfe";
reg = <0x48326000 0x2000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "vpfe0";
status = "disabled";
};
vpfe1: vpfe@48328000 {
compatible = "ti,am437x-vpfe";
reg = <0x48328000 0x2000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "vpfe1";
status = "disabled";
};
};
};
#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"

135
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -67,7 +67,13 @@
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&matrix_keypad_default>;
pinctrl-1 = <&matrix_keypad_sleep>;
linux,wakeup;
row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
@ -155,16 +161,23 @@
beeper: beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
pinctrl-0 = <&beeper_pins>;
pinctrl-0 = <&beeper_pins_default>;
pinctrl-1 = <&beeper_pins_sleep>;
gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
};
};
&am43xx_pinmux {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&wlan_pins_default>;
pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
pinctrl-1 = <&wlan_pins_sleep>;
ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
pinctrl-single,pins = <
0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
>;
};
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
@ -511,27 +524,121 @@
>;
};
uart0_pins_default: uart0_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
beeper_pins: beeper_pins {
beeper_pins_default: beeper_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
>;
};
beeper_pins_sleep: beeper_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */
>;
};
unused_pins: unused_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE)
AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
debugss_pins: pinmux_debugss_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
>;
};
uart0_pins_default: uart0_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart0_pins_sleep: uart0_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
matrix_keypad_default: matrix_keypad_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)
AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7)
AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
matrix_keypad_sleep: matrix_keypad_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7)
AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7)
AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_default>;
pinctrl-1 = <&uart0_pins_sleep>;
};
&i2c0 {

2505
arch/arm/boot/dts/am437x-l4.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

74
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -710,73 +710,123 @@
};
&prcm {
l4_wkup_cm: l4_wkup_cm@2800 {
wkup_cm: wkup-cm@2800 {
compatible = "ti,omap4-cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
l4_wkup_clkctrl: clk@20 {
l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
compatible = "ti,clkctrl";
reg = <0x20 0x34c>;
reg = <0x120 0x4>;
#clock-cells = <2>;
};
l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
compatible = "ti,clkctrl";
reg = <0x228 0xc>;
#clock-cells = <2>;
};
l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
compatible = "ti,clkctrl";
reg = <0x220 0x4>, <0x328 0x44>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@8300 {
mpu_cm: mpu-cm@8300 {
compatible = "ti,omap4-cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
mpu_clkctrl: clk@20 {
mpu_clkctrl: mpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@8400 {
gfx_l3_cm: gfx-l3-cm@8400 {
compatible = "ti,omap4-cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
gfx_l3_clkctrl: clk@20 {
gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@8500 {
l4_rtc_cm: l4-rtc-cm@8500 {
compatible = "ti,omap4-cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
l4_rtc_clkctrl: clk@20 {
l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l4_per_cm: l4_per_cm@8800 {
per_cm: per-cm@8800 {
compatible = "ti,omap4-cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
l4_per_clkctrl: clk@20 {
l3_clkctrl: l3-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xb04>;
reg = <0x20 0x3c>, <0x78 0x2c>;
#clock-cells = <2>;
};
l3s_clkctrl: l3s-clkctrl@68 {
compatible = "ti,clkctrl";
reg = <0x68 0xc>, <0x220 0x4c>;
#clock-cells = <2>;
};
pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
compatible = "ti,clkctrl";
reg = <0x320 0x4>;
#clock-cells = <2>;
};
l4ls_clkctrl: l4ls-clkctrl@420 {
compatible = "ti,clkctrl";
reg = <0x420 0x1a4>;
#clock-cells = <2>;
};
emif_clkctrl: emif-clkctrl@720 {
compatible = "ti,clkctrl";
reg = <0x720 0x4>;
#clock-cells = <2>;
};
dss_clkctrl: dss-clkctrl@a20 {
compatible = "ti,clkctrl";
reg = <0xa20 0x4>;
#clock-cells = <2>;
};
cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
compatible = "ti,clkctrl";
reg = <0xb20 0x4>;
#clock-cells = <2>;
};
};
};

2
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -555,7 +555,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

5
arch/arm/boot/dts/arm-realview-pbx.dtsi
View File

@ -44,7 +44,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
vmmc: fixedregulator@0 {
vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@ -52,7 +52,7 @@
regulator-boot-on;
};
veth: fixedregulator@0 {
veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
@ -567,4 +567,3 @@
};
};
};

2
arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
View File

@ -13,7 +13,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@80000000 {
reg = <0x80000000 0x40000000>;
};

368
arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts Normal file
View File

@ -0,0 +1,368 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
#include "aspeed-g5.dtsi"
/ {
model = "Facebook Backpack CMM BMC";
compatible = "facebook,cmm-bmc", "aspeed,ast2500";
aliases {
/*
* Override the default uart aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart3;
serial3 = &uart4;
/*
* Hardcode the bus number of i2c switches' channels to
* avoid breaking the legacy applications.
*/
i2c16 = &imux16;
i2c17 = &imux17;
i2c18 = &imux18;
i2c19 = &imux19;
i2c20 = &imux20;
i2c21 = &imux21;
i2c22 = &imux22;
i2c23 = &imux23;
i2c24 = &imux24;
i2c25 = &imux25;
i2c26 = &imux26;
i2c27 = &imux27;
i2c28 = &imux28;
i2c29 = &imux29;
i2c30 = &imux30;
i2c31 = &imux31;
i2c32 = &imux32;
i2c33 = &imux33;
i2c34 = &imux34;
i2c35 = &imux35;
i2c36 = &imux36;
i2c37 = &imux37;
i2c38 = &imux38;
i2c39 = &imux39;
};
chosen {
stdout-path = &uart1;
bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
&pinctrl {
aspeed,external-nodes = <&gfx &lhc>;
};
/*
* Update reset type to "system" (full chip) to fix warm reboot hang issue
* when reset type is set to default ("soc", gated by reset mask registers).
*/
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
/*
* wdt2 is not used by Backpack CMM.
*/
&wdt2 {
status = "disabled";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "facebook-bmc-flash-layout.dtsi"
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_ndsr1_default
&pinctrl_ndtr1_default
&pinctrl_nrts1_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default
&pinctrl_ncts3_default
&pinctrl_ndcd3_default
&pinctrl_nri3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
/*
* I2C bus reserved for communication with COM-E.
*/
&i2c0 {
status = "okay";
};
/*
* I2C bus to Line Cards and Fabric Cards.
*/
&i2c1 {
status = "okay";
i2c-switch@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
imux16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux20: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux21: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux22: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux23: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C bus to Power Distribution Board.
*/
&i2c2 {
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux28: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux29: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux30: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux31: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2c bus connected with temperature sensors on CMM.
*/
&i2c3 {
status = "okay";
};
/*
* I2C bus reserved for communication with COM-E.
*/
&i2c4 {
status = "okay";
};
/*
* I2c bus connected with ADM1278.
*/
&i2c5 {
status = "okay";
};
/*
* I2c bus connected with I/O Expander.
*/
&i2c6 {
status = "okay";
};
/*
* I2c bus connected with I/O Expander and EPROMs.
*/
&i2c7 {
status = "okay";
};
/*
* I2C bus to Fan Control Board.
*/
&i2c8 {
status = "okay";
i2c-switch@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
imux32: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux33: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux34: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux35: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux36: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux37: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux38: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux39: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C bus to CMM CPLD.
*/
&i2c13 {
status = "okay";
};
&adc {
status = "okay";
};

2
arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
View File

@ -13,7 +13,7 @@
bootargs = "earlyprintk";
};
memory {
memory@80000000 {
reg = <0x80000000 0x20000000>;
};

3
arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
View File

@ -14,7 +14,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@ -322,4 +322,3 @@
&adc {
status = "okay";
};

39
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
View File

@ -26,6 +26,16 @@
no-map;
reg = <0x5f000000 0x01000000>; /* 16M */
};
coldfire_memory: codefire_memory@5ee00000 {
reg = <0x5ee00000 0x00200000>;
no-map;
};
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x01000000>; /* 16MB */
};
};
leds {
@ -44,6 +54,22 @@
};
};
fsi: gpio-fsi {
compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
memory-region = <&coldfire_memory>;
aspeed,sram = <&sram>;
aspeed,cvic = <&cvic>;
clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
@ -169,6 +195,12 @@
status = "okay";
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi>;
};
&gpio {
pin_func_mode0 {
gpio-hog;
@ -303,13 +335,6 @@
line-name = "SYS_PWROK_BMC";
};
pin_gpio_h6 {
gpio-hog;
gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SCM1_FSI0_DATA_EN";
};
pin_gpio_h7 {
gpio-hog;
gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;

24
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
View File

@ -30,6 +30,11 @@
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
coldfire_memory: codefire_memory@9ef00000 {
reg = <0x9ef00000 0x00100000>;
no-map;
};
};
leds {
@ -49,11 +54,15 @@
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
no-gpio-delays;
memory-region = <&coldfire_memory>;
aspeed,sram = <&sram>;
aspeed,cvic = <&cvic>;
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
@ -76,6 +85,11 @@
linux,code = <ASPEED_GPIO(Q, 7)>;
};
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 12>;
};
};
&fmc {
@ -274,3 +288,11 @@
&ibt {
status = "okay";
};
&vhub {
status = "okay";
};
&adc {
status = "okay";
};

9
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
View File

@ -56,6 +56,11 @@
};
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 12>;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
@ -583,3 +588,7 @@
&ibt {
status = "okay";
};
&adc {
status = "okay";
};

2
arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
View File

@ -17,7 +17,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@80000000 {
reg = <0x80000000 0x20000000>;
};

8
arch/arm/boot/dts/at91-nattis-2-natte-2.dts
View File

@ -60,6 +60,8 @@
power-supply = <&bl_reg>;
enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_blon>;
};
panel: panel {
@ -164,6 +166,12 @@
(AT91_PINCTRL_OUTPUT |
AT91_PINCTRL_OUTPUT_VAL(0))>;
};
pinctrl_blon: blon {
atmel,pins = <AT91_PIOA 20 AT91_PERIPH_GPIO
(AT91_PINCTRL_OUTPUT |
AT91_PINCTRL_OUTPUT_VAL(0))>;
};
};
};

12
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -165,7 +165,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
atmel,fifo-size = <16>;
@ -211,7 +211,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&flx3_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
@ -223,7 +223,7 @@
compatible = "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&flx3_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
@ -240,7 +240,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&flx4_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
@ -252,7 +252,7 @@
compatible = "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&flx4_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
@ -268,7 +268,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx4_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;

2
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
View File

@ -197,7 +197,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;

4
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -258,7 +258,7 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&flx0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
@ -313,7 +313,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx4_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;

2
arch/arm/boot/dts/at91-sama5d4ek.dts
View File

@ -115,7 +115,7 @@
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck2>;
clocks = <&pmc PMC_TYPE_SYSTEM 10>;
clock-names = "mclk";
};

308
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -113,276 +113,28 @@
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91rm9200-clk-main";
#clock-cells = <0>;
clocks = <&main_osc>;
};
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
clk32k: slck {
compatible = "atmel,at91sam9260-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc>, <&slow_xtal>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
<150000000 240000000 2 1>;
};
pllb: pllbck {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
atmel,clk-input-range = <1000000 5000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
};
mck: masterck {
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 105000000>;
atmel,clk-divisors = <1 2 4 0>;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-usb";
#clock-cells = <0>;
atmel,clk-divisors = <1 2 4 0>;
clocks = <&pllb>;
};
prog: progck {
compatible = "atmel,at91rm9200-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
};
periphck {
compatible = "atmel,at91rm9200-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioA_clk: pioA_clk {
#clock-cells = <0>;
reg = <2>;
};
pioB_clk: pioB_clk {
#clock-cells = <0>;
reg = <3>;
};
pioC_clk: pioC_clk {
#clock-cells = <0>;
reg = <4>;
};
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <5>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <6>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <7>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <8>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <9>;
};
udc_clk: udc_clk {
#clock-cells = <0>;
reg = <10>;
};
twi0_clk: twi0_clk {
reg = <11>;
#clock-cells = <0>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <12>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <13>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <14>;
};
tc0_clk: tc0_clk {
#clock-cells = <0>;
reg = <17>;
};
tc1_clk: tc1_clk {
#clock-cells = <0>;
reg = <18>;
};
tc2_clk: tc2_clk {
#clock-cells = <0>;
reg = <19>;
};
ohci_clk: ohci_clk {
#clock-cells = <0>;
reg = <20>;
};
macb0_clk: macb0_clk {
#clock-cells = <0>;
reg = <21>;
};
isi_clk: isi_clk {
#clock-cells = <0>;
reg = <22>;
};
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <23>;
};
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <24>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <25>;
};
tc3_clk: tc3_clk {
#clock-cells = <0>;
reg = <26>;
};
tc4_clk: tc4_clk {
#clock-cells = <0>;
reg = <27>;
};
tc5_clk: tc5_clk {
#clock-cells = <0>;
reg = <28>;
};
};
#clock-cells = <2>;
clocks = <&slow_xtal>, <&main_xtal>;
clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
tcb0: timer@fffa0000 {
@ -393,7 +145,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@ -405,7 +157,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@ -746,7 +498,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@ -757,7 +509,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@ -768,7 +520,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@ -778,7 +530,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@ -791,7 +543,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
clocks = <&usart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@ -804,7 +556,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
clocks = <&usart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@ -817,7 +569,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
clocks = <&usart2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@ -830,7 +582,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
clocks = <&usart3_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
status = "disabled";
};
@ -843,7 +595,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "usart";
status = "disabled";
};
@ -856,7 +608,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "usart";
status = "disabled";
};
@ -867,7 +619,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
clocks = <&macb0_clk>, <&macb0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@ -876,7 +628,7 @@
compatible = "atmel,at91sam9260-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&udc_clk>, <&udpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@ -887,7 +639,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@ -898,7 +650,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
clocks = <&mci0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
};
@ -909,7 +661,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@ -922,7 +674,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "spi_clk";
status = "disabled";
};
@ -935,7 +687,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&spi1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@ -946,7 +698,7 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>, <&adc_op_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
@ -981,7 +733,7 @@
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
status = "disabled";
};
@ -989,7 +741,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@ -1007,7 +759,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@ -1027,7 +779,7 @@
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {

287
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -75,7 +75,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@ -86,7 +86,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
clocks = <&lcd_clk>, <&hclk1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>;
clock-names = "lcdc_clk", "hclk";
status = "disabled";
};
@ -106,7 +106,7 @@
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@ -132,7 +132,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@ -140,7 +140,7 @@
compatible = "atmel,at91sam9261-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&udc_clk>, <&udpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
atmel,matrix = <&matrix>;
status = "disabled";
@ -154,7 +154,7 @@
pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
};
@ -167,7 +167,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@ -179,7 +179,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
clocks = <&usart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@ -192,7 +192,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
clocks = <&usart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@ -205,7 +205,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
clocks = <&usart2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@ -216,7 +216,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@ -227,7 +227,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
clocks = <&ssc1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "pclk";
status = "disabled";
};
@ -238,7 +238,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
clocks = <&ssc2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@ -252,7 +252,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "spi_clk";
status = "disabled";
};
@ -265,7 +265,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&spi1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@ -299,7 +299,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@ -563,7 +563,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@ -574,7 +574,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@ -585,7 +585,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@ -593,250 +593,9 @@
compatible = "atmel,at91sam9261-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91rm9200-clk-main";
#clock-cells = <0>;
clocks = <&main_osc>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
<190000000 240000000 2 1>;
};
pllb: pllbck {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
atmel,clk-input-range = <1000000 5000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
};
mck: masterck {
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 0>;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-usb";
#clock-cells = <0>;
atmel,clk-divisors = <1 2 4 0>;
clocks = <&pllb>;
};
prog: progck {
compatible = "atmel,at91rm9200-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
prog2: prog2 {
#clock-cells = <0>;
reg = <2>;
interrupts = <AT91_PMC_PCKRDY(2)>;
};
prog3: prog3 {
#clock-cells = <0>;
reg = <3>;
interrupts = <AT91_PMC_PCKRDY(3)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
pck2: pck2 {
#clock-cells = <0>;
reg = <10>;
clocks = <&prog2>;
};
pck3: pck3 {
#clock-cells = <0>;
reg = <11>;
clocks = <&prog3>;
};
hclk0: hclk0 {
#clock-cells = <0>;
reg = <16>;
clocks = <&mck>;
};
hclk1: hclk1 {
#clock-cells = <0>;
reg = <17>;
clocks = <&mck>;
};
};
periphck {
compatible = "atmel,at91rm9200-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioA_clk: pioA_clk {
#clock-cells = <0>;
reg = <2>;
};
pioB_clk: pioB_clk {
#clock-cells = <0>;
reg = <3>;
};
pioC_clk: pioC_clk {
#clock-cells = <0>;
reg = <4>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <6>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <7>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <8>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <9>;
};
udc_clk: udc_clk {
#clock-cells = <0>;
reg = <10>;
};
twi0_clk: twi0_clk {
reg = <11>;
#clock-cells = <0>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <12>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <13>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <14>;
};
ssc1_clk: ssc1_clk {
#clock-cells = <0>;
reg = <15>;
};
ssc2_clk: ssc2_clk {
#clock-cells = <0>;
reg = <16>;
};
tc0_clk: tc0_clk {
#clock-cells = <0>;
reg = <17>;
};
tc1_clk: tc1_clk {
#clock-cells = <0>;
reg = <18>;
};
tc2_clk: tc2_clk {
#clock-cells = <0>;
reg = <19>;
};
ohci_clk: ohci_clk {
#clock-cells = <0>;
reg = <20>;
};
lcd_clk: lcd_clk {
#clock-cells = <0>;
reg = <21>;
};
};
#clock-cells = <2>;
clocks = <&slow_xtal>, <&main_xtal>;
clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
@ -855,7 +614,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
rtc@fffffd20 {

315
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -96,264 +96,9 @@
compatible = "atmel,at91sam9263-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91rm9200-clk-main";
#clock-cells = <0>;
clocks = <&main_osc>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
<190000000 240000000 2 1>;
};
pllb: pllbck {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
<190000000 240000000 2 1>;
};
mck: masterck {
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 120000000>;
atmel,clk-divisors = <1 2 4 0>;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-usb";
#clock-cells = <0>;
atmel,clk-divisors = <1 2 4 0>;
clocks = <&pllb>;
};
prog: progck {
compatible = "atmel,at91rm9200-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
prog2: prog2 {
#clock-cells = <0>;
reg = <2>;
interrupts = <AT91_PMC_PCKRDY(2)>;
};
prog3: prog3 {
#clock-cells = <0>;
reg = <3>;
interrupts = <AT91_PMC_PCKRDY(3)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
pck2: pck2 {
#clock-cells = <0>;
reg = <10>;
clocks = <&prog2>;
};
pck3: pck3 {
#clock-cells = <0>;
reg = <11>;
clocks = <&prog3>;
};
};
periphck {
compatible = "atmel,at91rm9200-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioA_clk: pioA_clk {
#clock-cells = <0>;
reg = <2>;
};
pioB_clk: pioB_clk {
#clock-cells = <0>;
reg = <3>;
};
pioCDE_clk: pioCDE_clk {
#clock-cells = <0>;
reg = <4>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <7>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <8>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <9>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <10>;
};
mci1_clk: mci1_clk {
#clock-cells = <0>;
reg = <11>;
};
can_clk: can_clk {
#clock-cells = <0>;
reg = <12>;
};
twi0_clk: twi0_clk {
#clock-cells = <0>;
reg = <13>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <14>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <15>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <16>;
};
ssc1_clk: ssc1_clk {
#clock-cells = <0>;
reg = <17>;
};
ac97_clk: ac97_clk {
#clock-cells = <0>;
reg = <18>;
};
tcb_clk: tcb_clk {
#clock-cells = <0>;
reg = <19>;
};
pwm_clk: pwm_clk {
#clock-cells = <0>;
reg = <20>;
};
macb0_clk: macb0_clk {
#clock-cells = <0>;
reg = <21>;
};
g2de_clk: g2de_clk {
#clock-cells = <0>;
reg = <23>;
};
udc_clk: udc_clk {
#clock-cells = <0>;
reg = <24>;
};
isi_clk: isi_clk {
#clock-cells = <0>;
reg = <25>;
};
lcd_clk: lcd_clk {
#clock-cells = <0>;
reg = <26>;
};
dma_clk: dma_clk {
#clock-cells = <0>;
reg = <27>;
};
ohci_clk: ohci_clk {
#clock-cells = <0>;
reg = <29>;
};
};
#clock-cells = <2>;
clocks = <&slow_xtal>, <&main_xtal>;
clock-names = "slow_xtal", "main_xtal";
};
ramc0: ramc@ffffe200 {
@ -385,7 +130,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
tcb0: timer@fff7c000 {
@ -394,7 +139,7 @@
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb_clk>, <&slow_xtal>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "slow_clk";
};
@ -736,7 +481,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff400 {
@ -747,7 +492,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff600 {
@ -758,7 +503,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffff800 {
@ -769,7 +514,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioE: gpio@fffffa00 {
@ -780,7 +525,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
};
@ -790,7 +535,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@ -803,7 +548,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
clocks = <&usart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@ -816,7 +561,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
clocks = <&usart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@ -829,7 +574,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
clocks = <&usart2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@ -840,7 +585,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@ -851,7 +596,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
clocks = <&ssc1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
clock-names = "pclk";
status = "disabled";
};
@ -862,7 +607,7 @@
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ac97>;
clocks = <&ac97_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
clock-names = "ac97_clk";
status = "disabled";
};
@ -873,7 +618,7 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
clocks = <&macb0_clk>, <&macb0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@ -882,7 +627,7 @@
compatible = "atmel,at91sam9263-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&udc_clk>, <&udpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@ -893,7 +638,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
status = "disabled";
};
@ -904,7 +649,7 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
status = "disabled";
};
@ -916,7 +661,7 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mci1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
clock-names = "mci_clk";
status = "disabled";
};
@ -940,7 +685,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@ -953,7 +698,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&spi1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "spi_clk";
status = "disabled";
};
@ -963,7 +708,7 @@
reg = <0xfffb8000 0x300>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
clocks = <&pwm_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "pwm_clk";
status = "disabled";
};
@ -974,7 +719,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_rx_tx>;
clocks = <&can_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "can_clk";
};
@ -1007,7 +752,7 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
clocks = <&lcd_clk>, <&lcd_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "lcdc_clk", "hclk";
status = "disabled";
};
@ -1016,7 +761,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@ -1034,7 +779,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller0: nand-controller {
@ -1055,7 +800,7 @@
reg = <0x80000000 0x20000000>;
ranges = <0x0 0x0 0x80000000 0x10000000
0x1 0x0 0x90000000 0x10000000>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller1: nand-controller {

4
arch/arm/boot/dts/at91sam9g15.dtsi
View File

@ -24,6 +24,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
};
};

23
arch/arm/boot/dts/at91sam9g20.dtsi
View File

@ -40,28 +40,7 @@
};
pmc: pmc@fffffc00 {
plla: pllack {
atmel,clk-input-range = <2000000 32000000>;
atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
<695000000 750000000 1 0>,
<645000000 700000000 2 0>,
<595000000 650000000 3 0>,
<545000000 600000000 0 1>,
<495000000 550000000 1 1>,
<445000000 500000000 2 1>,
<400000000 450000000 3 1>;
};
pllb: pllbck {
compatible = "atmel,at91sam9g20-clk-pllb";
atmel,clk-input-range = <2000000 32000000>;
atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
};
mck: masterck {
atmel,clk-output-range = <0 133000000>;
atmel,clk-divisors = <1 2 4 6>;
};
compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon";
};
};
};

4
arch/arm/boot/dts/at91sam9g25.dtsi
View File

@ -26,6 +26,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
};
};

4
arch/arm/boot/dts/at91sam9g25ek.dts
View File

@ -32,9 +32,9 @@
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
clocks = <&pck0>;
clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "xvclk";
assigned-clocks = <&pck0>;
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
assigned-clock-rates = <25000000>;
status = "okay";

4
arch/arm/boot/dts/at91sam9g35.dtsi
View File

@ -25,6 +25,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
};
};

239
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -88,7 +88,7 @@
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
clocks = <&lcd_clk>, <&lcd_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "lcdc_clk";
status = "disabled";
};
@ -106,7 +106,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@ -132,7 +132,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@ -143,7 +143,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
clocks = <&mci0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
status = "disabled";
};
@ -154,7 +154,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@ -175,7 +175,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
clocks = <&usart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@ -188,7 +188,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
clocks = <&usart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@ -201,7 +201,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
clocks = <&usart2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@ -214,7 +214,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
clocks = <&usart3_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@ -242,7 +242,7 @@
reg = <0xfffc8000 0x300>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
clocks = <&pwm_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "pwm_clk";
status = "disabled";
};
@ -255,7 +255,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@ -266,7 +266,7 @@
compatible = "atmel,at91sam9rl-adc";
reg = <0xfffd0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>, <&adc_op_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0x3f>;
@ -304,7 +304,7 @@
reg = <0x00600000 0x100000>,
<0xfffd4000 0x4000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&udphs_clk>, <&utmi>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
@ -366,7 +366,7 @@
reg = <0xffffe600 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
clocks = <&dma0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@ -399,7 +399,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@ -794,7 +794,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@ -805,7 +805,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@ -816,7 +816,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffffa00 {
@ -827,7 +827,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
};
@ -835,202 +835,9 @@
compatible = "atmel,at91sam9rl-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main: mainck {
compatible = "atmel,at91rm9200-clk-main";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <3>;
atmel,pll-clk-output-ranges = <80000000 200000000 0>,
<190000000 240000000 2>;
};
utmi: utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_LOCKU>;
clocks = <&main>;
};
mck: masterck {
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 0>;
};
prog: progck {
compatible = "atmel,at91rm9200-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
};
periphck {
compatible = "atmel,at91rm9200-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioA_clk: pioA_clk {
#clock-cells = <0>;
reg = <2>;
};
pioB_clk: pioB_clk {
#clock-cells = <0>;
reg = <3>;
};
pioC_clk: pioC_clk {
#clock-cells = <0>;
reg = <4>;
};
pioD_clk: pioD_clk {
#clock-cells = <0>;
reg = <5>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <6>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <7>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <8>;
};
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <9>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <10>;
};
twi0_clk: twi0_clk {
#clock-cells = <0>;
reg = <11>;
};
twi1_clk: twi1_clk {
#clock-cells = <0>;
reg = <12>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <13>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <14>;
};
ssc1_clk: ssc1_clk {
#clock-cells = <0>;
reg = <15>;
};
tc0_clk: tc0_clk {
#clock-cells = <0>;
reg = <16>;
};
tc1_clk: tc1_clk {
#clock-cells = <0>;
reg = <17>;
};
tc2_clk: tc2_clk {
#clock-cells = <0>;
reg = <18>;
};
pwm_clk: pwm_clk {
#clock-cells = <0>;
reg = <19>;
};
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <20>;
};
dma0_clk: dma0_clk {
#clock-cells = <0>;
reg = <21>;
};
udphs_clk: udphs_clk {
#clock-cells = <0>;
reg = <22>;
};
lcd_clk: lcd_clk {
#clock-cells = <0>;
reg = <23>;
};
};
#clock-cells = <2>;
clocks = <&clk32k>, <&main_xtal>;
clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
@ -1049,7 +856,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
watchdog@fffffd40 {

4
arch/arm/boot/dts/at91sam9x25.dtsi
View File

@ -27,6 +27,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
};
};

4
arch/arm/boot/dts/at91sam9x35.dtsi
View File

@ -26,6 +26,10 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
};
};

326
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -111,7 +111,7 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&ddrck>;
clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
@ -124,269 +124,9 @@
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
clock-frequency = <12000000>;
clock-accuracy = <50000000>;
};
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
clocks = <&main_rc_osc>, <&main_osc>;
};
plla: pllack {
compatible = "atmel,at91rm9200-clk-pll";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <2000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <745000000 800000000 0 0
695000000 750000000 1 0
645000000 700000000 2 0
595000000 650000000 3 0
545000000 600000000 0 1
495000000 555000000 1 1
445000000 500000000 2 1
400000000 450000000 3 1>;
};
plladiv: plladivck {
compatible = "atmel,at91sam9x5-clk-plldiv";
#clock-cells = <0>;
clocks = <&plla>;
};
utmi: utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_LOCKU>;
clocks = <&main>;
};
mck: masterck {
compatible = "atmel,at91sam9x5-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
atmel,master-clk-have-div3-pres;
};
usb: usbck {
compatible = "atmel,at91sam9x5-clk-usb";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
prog: progck {
compatible = "atmel,at91sam9x5-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
};
smd: smdclk {
compatible = "atmel,at91sam9x5-clk-smd";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
ddrck: ddrck {
#clock-cells = <0>;
reg = <2>;
clocks = <&mck>;
};
smdck: smdck {
#clock-cells = <0>;
reg = <4>;
clocks = <&smd>;
};
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck: udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
};
periphck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioAB_clk: pioAB_clk {
#clock-cells = <0>;
reg = <2>;
};
pioCD_clk: pioCD_clk {
#clock-cells = <0>;
reg = <3>;
};
smd_clk: smd_clk {
#clock-cells = <0>;
reg = <4>;
};
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <5>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <6>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <7>;
};
twi0_clk: twi0_clk {
reg = <9>;
#clock-cells = <0>;
};
twi1_clk: twi1_clk {
#clock-cells = <0>;
reg = <10>;
};
twi2_clk: twi2_clk {
#clock-cells = <0>;
reg = <11>;
};
mci0_clk: mci0_clk {
#clock-cells = <0>;
reg = <12>;
};
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <13>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <14>;
};
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <15>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <16>;
};
tcb0_clk: tcb0_clk {
#clock-cells = <0>;
reg = <17>;
};
pwm_clk: pwm_clk {
#clock-cells = <0>;
reg = <18>;
};
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <19>;
};
dma0_clk: dma0_clk {
#clock-cells = <0>;
reg = <20>;
};
dma1_clk: dma1_clk {
#clock-cells = <0>;
reg = <21>;
};
uhphs_clk: uhphs_clk {
#clock-cells = <0>;
reg = <22>;
};
udphs_clk: udphs_clk {
#clock-cells = <0>;
reg = <23>;
};
mci1_clk: mci1_clk {
#clock-cells = <0>;
reg = <26>;
};
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <28>;
};
};
#clock-cells = <2>;
clocks = <&clk32k>, <&main_xtal>;
clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
@ -405,7 +145,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
sckc@fffffe50 {
@ -438,7 +178,7 @@
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@ -448,7 +188,7 @@
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@ -457,7 +197,7 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
clocks = <&dma0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "dma_clk";
};
@ -466,7 +206,7 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
clocks = <&dma1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@ -864,7 +604,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@ -876,7 +616,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioC: gpio@fffff800 {
@ -887,7 +627,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioD: gpio@fffffa00 {
@ -899,7 +639,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
};
@ -912,7 +652,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "pclk";
status = "disabled";
};
@ -924,7 +664,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
clocks = <&mci0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@ -938,7 +678,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
pinctrl-names = "default";
clocks = <&mci1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@ -954,7 +694,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@ -968,7 +708,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
clocks = <&usart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "usart";
status = "disabled";
};
@ -982,7 +722,7 @@
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
<&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
clocks = <&usart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@ -996,7 +736,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
clocks = <&usart2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@ -1012,7 +752,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&twi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
status = "disabled";
};
@ -1027,7 +767,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&twi1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
status = "disabled";
};
@ -1042,7 +782,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&twi2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
status = "disabled";
};
@ -1052,7 +792,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "usart";
status = "disabled";
};
@ -1063,7 +803,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "usart";
status = "disabled";
};
@ -1074,7 +814,7 @@
compatible = "atmel,at91sam9x5-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>,
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>,
<&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
@ -1121,7 +861,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&spi0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@ -1137,7 +877,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&spi1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@ -1149,7 +889,7 @@
reg = <0x00500000 0x80000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&utmi>, <&udphs_clk>;
clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "pclk";
status = "disabled";
@ -1229,7 +969,7 @@
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
clocks = <&pwm_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
#pwm-cells = <3>;
status = "disabled";
};
@ -1239,7 +979,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@ -1248,7 +988,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&utmi>, <&uhphs_clk>;
clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@ -1266,7 +1006,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
clocks = <&mck>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {

18
arch/arm/boot/dts/at91sam9x5_can.dtsi
View File

@ -13,27 +13,13 @@
/ {
ahb {
apb {
pmc: pmc@fffffc00 {
periphck {
can0_clk: can0_clk {
#clock-cells = <0>;
reg = <29>;
};
can1_clk: can1_clk {
#clock-cells = <0>;
reg = <30>;
};
};
};
can0: can@f8000000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8000000 0x300>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
clocks = <&can0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
clock-names = "can_clk";
status = "disabled";
};
@ -44,7 +30,7 @@
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
clocks = <&can1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
clock-names = "can_clk";
status = "disabled";
};

11
arch/arm/boot/dts/at91sam9x5_isi.dtsi
View File

@ -44,22 +44,13 @@
};
};
pmc: pmc@fffffc00 {
periphck {
isi_clk: isi_clk {
#clock-cells = <0>;
reg = <25>;
};
};
};
isi: isi@f8048000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf8048000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
clocks = <&isi_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "isi_clk";
status = "disabled";
port {

19
arch/arm/boot/dts/at91sam9x5_lcd.dtsi
View File

@ -17,7 +17,7 @@
compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
@ -143,23 +143,6 @@
};
};
};
pmc: pmc@fffffc00 {
periphck {
lcdc_clk: lcdc_clk {
#clock-cells = <0>;
reg = <25>;
};
};
systemck {
lcdck: lcdck {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
};
};
};
};
};

11
arch/arm/boot/dts/at91sam9x5_macb0.dtsi
View File

@ -43,22 +43,13 @@
};
};
pmc: pmc@fffffc00 {
periphck {
macb0_clk: macb0_clk {
#clock-cells = <0>;
reg = <24>;
};
};
};
macb0: ethernet@f802c000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
clocks = <&macb0_clk>, <&macb0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "hclk", "pclk";
status = "disabled";
};

11
arch/arm/boot/dts/at91sam9x5_macb1.dtsi
View File

@ -31,22 +31,13 @@
};
};
pmc: pmc@fffffc00 {
periphck {
macb1_clk: macb1_clk {
#clock-cells = <0>;
reg = <27>;
};
};
};
macb1: ethernet@f8030000 {
compatible = "cdns,at91sam9260-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
clocks = <&macb1_clk>, <&macb1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "hclk", "pclk";
status = "disabled";
};

11
arch/arm/boot/dts/at91sam9x5_usart3.dtsi
View File

@ -42,15 +42,6 @@
};
};
pmc: pmc@fffffc00 {
periphck {
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <8>;
};
};
};
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
@ -60,7 +51,7 @@
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
clocks = <&usart3_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};

5
arch/arm/boot/dts/axp81x.dtsi
View File

@ -48,6 +48,11 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
compatible = "x-powers,axp813-ac-power-supply";
status = "disabled";
};
axp_adc: adc {
compatible = "x-powers,axp813-adc";
#io-channel-cells = <1>;

8
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -41,6 +41,14 @@
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
ethernet0 = &amac0;
ethernet1 = &amac1;
ethernet2 = &amac2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

8
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@ -1,12 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;

8
arch/arm/boot/dts/bcm2835-rpi-zero.dts
View File

@ -1,12 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Stefan Wahren <stefan.wahren@i2se.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;

4
arch/arm/boot/dts/bcm2835-rpi.dtsi
View File

@ -30,9 +30,9 @@
#power-domain-cells = <1>;
};
mailbox@7e00b840 {
vchiq: mailbox@7e00b840 {
compatible = "brcm,bcm2835-vchiq";
reg = <0x7e00b840 0xf>;
reg = <0x7e00b840 0x3c>;
interrupts = <0 2>;
};
};

2
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2836.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"

6
arch/arm/boot/dts/bcm2836-rpi.dtsi Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm2835-rpi.dtsi"
&vchiq {
compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq";
};

2
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"

2
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"

2
arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm2836-rpi.dtsi"
/ {
memory {

45
arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
* Copyright (C) 2018 Rene Kjellerup <rk.katana.steel@gmail.com>
*/
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "linksys,ea6500-v2", "brcm,bcm4708";
model = "Linksys EA6500 V2";
chosen {
bootargs = "console=ttyS0,115200";
};
memory {
reg = <0x00000000 0x08000000>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
};
};
&usb3_phy {
status = "okay";
};

13
arch/arm/boot/dts/bcm47081.dtsi
View File

@ -1,20 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for BCM47081 SoC.
*
* Copyright © 2014 Rafał Miłecki <zajec5@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "bcm5301x.dtsi"

3
arch/arm/boot/dts/bcm4709.dtsi
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
*
* Licensed under the ISC license.
*/
#include "bcm4708.dtsi"

3
arch/arm/boot/dts/bcm47094.dtsi
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
*
* Licensed under the ISC license.
*/
#include "bcm4708.dtsi"

3
arch/arm/boot/dts/bcm47189-tenda-ac9.dts
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
*
* Licensed under the ISC license.
*/
/dts-v1/;

44
arch/arm/boot/dts/bcm5301x.dtsi
View File

@ -37,6 +37,8 @@
reg = <0x0400 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart1>;
status = "disabled";
};
};
@ -391,6 +393,48 @@
status = "disabled";
};
dmu@1800c000 {
compatible = "simple-bus";
ranges = <0 0x1800c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
cru@100 {
compatible = "simple-bus";
reg = <0x100 0x1a4>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
pin-controller@1c0 {
compatible = "brcm,bcm4708-pinmux";
reg = <0x1c0 0x24>;
reg-names = "cru_gpio_control";
spi-pins {
groups = "spi_grp";
function = "spi";
};
i2c {
groups = "i2c_grp";
function = "i2c";
};
pwm {
groups = "pwm0_grp", "pwm1_grp",
"pwm2_grp", "pwm3_grp";
function = "pwm";
};
pinmux_uart1: uart1 {
groups = "uart1_grp";
function = "uart1";
};
};
};
};
lcpll0: lcpll0@1800c100 {
#clock-cells = <1>;
compatible = "brcm,nsp-lcpll0";

3
arch/arm/boot/dts/bcm53573.dtsi
View File

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
*
* Licensed under the ISC license.
*/
#include <dt-bindings/gpio/gpio.h>

31
arch/arm/boot/dts/bcm63138.dtsi
View File

@ -143,6 +143,37 @@
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
ahci: sata@8000 {
compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0xa000 0x9ac>, <0x8040 0x24>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&pmb0 3 1>;
reset-names = "ahci";
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
};
};
sata_phy: sata-phy@8100 {
compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
reg = <0x8100 0x1e00>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
};
/* Legacy UBUS base */

4
arch/arm/boot/dts/bcm958522er.dts
View File

@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958522ER)";
compatible = "brcm,bcm58522", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};

4
arch/arm/boot/dts/bcm958525er.dts
View File

@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958525ER)";
compatible = "brcm,bcm58525", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};

4
arch/arm/boot/dts/bcm958525xmc.dts
View File

@ -39,10 +39,6 @@
model = "NorthStar Plus XMC (BCM958525xmc)";
compatible = "brcm,bcm58525", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};

4
arch/arm/boot/dts/bcm958622hr.dts
View File

@ -39,10 +39,6 @@
model = "NorthStar Plus SVK (BCM958622HR)";
compatible = "brcm,bcm58622", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};

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