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OMAPDSS: remove unused old clock calculation code
Now that the old clock calculation code is no longer used, we can remove it from the driver. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
parent
f1e0001f97
commit
b7ec96c78b
@ -3311,54 +3311,6 @@ static void dispc_dump_regs(struct seq_file *s)
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#undef DUMPREG
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}
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/* with fck as input clock rate, find dispc dividers that produce req_pck */
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void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
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struct dispc_clock_info *cinfo)
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{
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u16 pcd_min, pcd_max;
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unsigned long best_pck;
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u16 best_ld, cur_ld;
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u16 best_pd, cur_pd;
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pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
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pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
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best_pck = 0;
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best_ld = 0;
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best_pd = 0;
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for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
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unsigned long lck = fck / cur_ld;
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for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
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unsigned long pck = lck / cur_pd;
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long old_delta = abs(best_pck - req_pck);
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long new_delta = abs(pck - req_pck);
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if (best_pck == 0 || new_delta < old_delta) {
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best_pck = pck;
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best_ld = cur_ld;
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best_pd = cur_pd;
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if (pck == req_pck)
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goto found;
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}
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if (pck < req_pck)
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break;
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}
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if (lck / pcd_min < req_pck)
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break;
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}
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found:
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cinfo->lck_div = best_ld;
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cinfo->pck_div = best_pd;
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cinfo->lck = fck / cinfo->lck_div;
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cinfo->pck = cinfo->lck / cinfo->pck_div;
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}
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/* calculate clock rates using dividers in cinfo */
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int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
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struct dispc_clock_info *cinfo)
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@ -1430,190 +1430,6 @@ static int dsi_calc_clock_rates(struct platform_device *dsidev,
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return 0;
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}
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int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
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unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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struct dsi_clock_info cur, best;
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struct dispc_clock_info best_dispc;
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int min_fck_per_pck;
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int match = 0;
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unsigned long dss_sys_clk, max_dss_fck;
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dss_sys_clk = clk_get_rate(dsi->sys_clk);
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max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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if (req_pck == dsi->cache_req_pck &&
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dsi->cache_cinfo.clkin == dss_sys_clk) {
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DSSDBG("DSI clock info found from cache\n");
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*dsi_cinfo = dsi->cache_cinfo;
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dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
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dispc_cinfo);
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return 0;
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}
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > max_dss_fck) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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min_fck_per_pck = 0;
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}
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DSSDBG("dsi_pll_calc\n");
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retry:
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memset(&best, 0, sizeof(best));
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memset(&best_dispc, 0, sizeof(best_dispc));
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memset(&cur, 0, sizeof(cur));
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cur.clkin = dss_sys_clk;
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/* 0.75MHz < Fint = clkin / regn < 2.1MHz */
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/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
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for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
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cur.fint = cur.clkin / cur.regn;
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if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
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continue;
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/* DSIPHY(MHz) = (2 * regm / regn) * clkin */
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for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
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unsigned long a, b;
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a = 2 * cur.regm * (cur.clkin/1000);
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b = cur.regn;
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cur.clkin4ddr = a / b * 1000;
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if (cur.clkin4ddr > 1800 * 1000 * 1000)
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break;
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/* dsi_pll_hsdiv_dispc_clk(MHz) =
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* DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
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for (cur.regm_dispc = 1; cur.regm_dispc <
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dsi->regm_dispc_max; ++cur.regm_dispc) {
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struct dispc_clock_info cur_dispc;
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cur.dsi_pll_hsdiv_dispc_clk =
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cur.clkin4ddr / cur.regm_dispc;
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if (cur.regm_dispc > 1 &&
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cur.regm_dispc % 2 != 0 &&
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req_pck >= 1000000)
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continue;
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/* this will narrow down the search a bit,
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* but still give pixclocks below what was
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* requested */
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if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
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break;
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if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
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continue;
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if (min_fck_per_pck &&
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cur.dsi_pll_hsdiv_dispc_clk <
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req_pck * min_fck_per_pck)
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continue;
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match = 1;
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dispc_find_clk_divs(req_pck,
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cur.dsi_pll_hsdiv_dispc_clk,
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&cur_dispc);
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if (abs(cur_dispc.pck - req_pck) <
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abs(best_dispc.pck - req_pck)) {
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best = cur;
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best_dispc = cur_dispc;
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if (cur_dispc.pck == req_pck)
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goto found;
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}
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}
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}
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}
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found:
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if (!match) {
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if (min_fck_per_pck) {
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DSSERR("Could not find suitable clock settings.\n"
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"Turning FCK/PCK constraint off and"
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"trying again.\n");
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min_fck_per_pck = 0;
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goto retry;
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}
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DSSERR("Could not find suitable clock settings.\n");
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return -EINVAL;
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}
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/* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
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best.regm_dsi = 0;
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best.dsi_pll_hsdiv_dsi_clk = 0;
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if (dsi_cinfo)
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*dsi_cinfo = best;
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if (dispc_cinfo)
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*dispc_cinfo = best_dispc;
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dsi->cache_req_pck = req_pck;
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dsi->cache_clk_freq = 0;
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dsi->cache_cinfo = best;
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return 0;
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}
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static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
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unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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struct dsi_clock_info cur, best;
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DSSDBG("dsi_pll_calc_ddrfreq\n");
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memset(&best, 0, sizeof(best));
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memset(&cur, 0, sizeof(cur));
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cur.clkin = clk_get_rate(dsi->sys_clk);
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for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
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cur.fint = cur.clkin / cur.regn;
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if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
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continue;
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/* DSIPHY(MHz) = (2 * regm / regn) * clkin */
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for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
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unsigned long a, b;
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a = 2 * cur.regm * (cur.clkin/1000);
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b = cur.regn;
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cur.clkin4ddr = a / b * 1000;
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if (cur.clkin4ddr > 1800 * 1000 * 1000)
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break;
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if (abs(cur.clkin4ddr - req_clkin4ddr) <
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abs(best.clkin4ddr - req_clkin4ddr)) {
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best = cur;
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DSSDBG("best %ld\n", best.clkin4ddr);
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}
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if (cur.clkin4ddr == req_clkin4ddr)
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goto found;
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}
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}
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found:
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if (cinfo)
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*cinfo = best;
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return 0;
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}
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static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
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{
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unsigned long max_dsi_fck;
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@ -1624,90 +1440,6 @@ static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
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cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
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}
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static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
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unsigned long req_pck, struct dsi_clock_info *cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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unsigned regm_dispc, best_regm_dispc;
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unsigned long dispc_clk, best_dispc_clk;
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int min_fck_per_pck;
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unsigned long max_dss_fck;
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struct dispc_clock_info best_dispc;
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bool match;
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max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > max_dss_fck) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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min_fck_per_pck = 0;
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}
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retry:
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best_regm_dispc = 0;
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best_dispc_clk = 0;
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memset(&best_dispc, 0, sizeof(best_dispc));
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match = false;
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for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
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struct dispc_clock_info cur_dispc;
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dispc_clk = cinfo->clkin4ddr / regm_dispc;
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/* this will narrow down the search a bit,
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* but still give pixclocks below what was
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* requested */
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if (dispc_clk < req_pck)
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break;
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if (dispc_clk > max_dss_fck)
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continue;
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if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
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continue;
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match = true;
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dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
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if (abs(cur_dispc.pck - req_pck) <
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abs(best_dispc.pck - req_pck)) {
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best_regm_dispc = regm_dispc;
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best_dispc_clk = dispc_clk;
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best_dispc = cur_dispc;
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if (cur_dispc.pck == req_pck)
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goto found;
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}
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}
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if (!match) {
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if (min_fck_per_pck) {
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DSSERR("Could not find suitable clock settings.\n"
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"Turning FCK/PCK constraint off and"
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"trying again.\n");
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min_fck_per_pck = 0;
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goto retry;
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}
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DSSERR("Could not find suitable clock settings.\n");
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return -EINVAL;
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}
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found:
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cinfo->regm_dispc = best_regm_dispc;
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cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
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*dispc_cinfo = best_dispc;
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return 0;
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}
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int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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{
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@ -4384,55 +4116,6 @@ int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
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}
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EXPORT_SYMBOL(omapdss_dsi_configure_pins);
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static int dsi_set_clocks(struct omap_dss_device *dssdev,
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unsigned long ddr_clk, unsigned long lp_clk)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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struct dsi_clock_info cinfo;
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struct dispc_clock_info dispc_cinfo;
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unsigned lp_clk_div;
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unsigned long dsi_fclk;
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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unsigned long pck;
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int r;
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DSSDBG("Setting DSI clocks: ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
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/* Calculate PLL output clock */
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r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
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if (r)
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goto err;
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/* Calculate PLL's DSI clock */
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dsi_pll_calc_dsi_fck(&cinfo);
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/* Calculate PLL's DISPC clock and pck & lck divs */
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pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
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DSSDBG("finding dispc dividers for pck %lu\n", pck);
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r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
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if (r)
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goto err;
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/* Calculate LP clock */
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dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
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lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
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dsi->user_dsi_cinfo.regn = cinfo.regn;
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dsi->user_dsi_cinfo.regm = cinfo.regm;
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dsi->user_dsi_cinfo.regm_dispc = cinfo.regm_dispc;
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dsi->user_dsi_cinfo.regm_dsi = cinfo.regm_dsi;
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dsi->user_dsi_cinfo.lp_clk_div = lp_clk_div;
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dsi->user_dispc_cinfo.lck_div = dispc_cinfo.lck_div;
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dsi->user_dispc_cinfo.pck_div = dispc_cinfo.pck_div;
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return 0;
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err:
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return r;
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}
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int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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@ -581,121 +581,6 @@ static int dss_setup_default_clock(void)
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return 0;
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}
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int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
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struct dispc_clock_info *dispc_cinfo)
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{
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unsigned long prate;
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struct dss_clock_info best_dss;
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struct dispc_clock_info best_dispc;
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unsigned long fck, max_dss_fck;
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u16 fck_div;
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int match = 0;
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int min_fck_per_pck;
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prate = dss_get_dpll4_rate();
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max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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fck = clk_get_rate(dss.dss_clk);
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if (req_pck == dss.cache_req_pck && prate == dss.cache_prate &&
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dss.cache_dss_cinfo.fck == fck) {
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DSSDBG("dispc clock info found from cache.\n");
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*dss_cinfo = dss.cache_dss_cinfo;
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*dispc_cinfo = dss.cache_dispc_cinfo;
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return 0;
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}
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > max_dss_fck) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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min_fck_per_pck = 0;
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}
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retry:
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memset(&best_dss, 0, sizeof(best_dss));
|
||||
memset(&best_dispc, 0, sizeof(best_dispc));
|
||||
|
||||
if (dss.dpll4_m4_ck == NULL) {
|
||||
struct dispc_clock_info cur_dispc;
|
||||
/* XXX can we change the clock on omap2? */
|
||||
fck = clk_get_rate(dss.dss_clk);
|
||||
fck_div = 1;
|
||||
|
||||
dispc_find_clk_divs(req_pck, fck, &cur_dispc);
|
||||
match = 1;
|
||||
|
||||
best_dss.fck = fck;
|
||||
best_dss.fck_div = fck_div;
|
||||
|
||||
best_dispc = cur_dispc;
|
||||
|
||||
goto found;
|
||||
} else {
|
||||
for (fck_div = dss.feat->fck_div_max; fck_div > 0; --fck_div) {
|
||||
struct dispc_clock_info cur_dispc;
|
||||
|
||||
fck = prate / fck_div * dss.feat->dss_fck_multiplier;
|
||||
|
||||
if (fck > max_dss_fck)
|
||||
continue;
|
||||
|
||||
if (min_fck_per_pck &&
|
||||
fck < req_pck * min_fck_per_pck)
|
||||
continue;
|
||||
|
||||
match = 1;
|
||||
|
||||
dispc_find_clk_divs(req_pck, fck, &cur_dispc);
|
||||
|
||||
if (abs(cur_dispc.pck - req_pck) <
|
||||
abs(best_dispc.pck - req_pck)) {
|
||||
|
||||
best_dss.fck = fck;
|
||||
best_dss.fck_div = fck_div;
|
||||
|
||||
best_dispc = cur_dispc;
|
||||
|
||||
if (cur_dispc.pck == req_pck)
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
found:
|
||||
if (!match) {
|
||||
if (min_fck_per_pck) {
|
||||
DSSERR("Could not find suitable clock settings.\n"
|
||||
"Turning FCK/PCK constraint off and"
|
||||
"trying again.\n");
|
||||
min_fck_per_pck = 0;
|
||||
goto retry;
|
||||
}
|
||||
|
||||
DSSERR("Could not find suitable clock settings.\n");
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (dss_cinfo)
|
||||
*dss_cinfo = best_dss;
|
||||
if (dispc_cinfo)
|
||||
*dispc_cinfo = best_dispc;
|
||||
|
||||
dss.cache_req_pck = req_pck;
|
||||
dss.cache_prate = prate;
|
||||
dss.cache_dss_cinfo = best_dss;
|
||||
dss.cache_dispc_cinfo = best_dispc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dss_set_venc_output(enum omap_dss_venc_type type)
|
||||
{
|
||||
int l = 0;
|
||||
|
||||
@ -268,8 +268,6 @@ void dss_set_dac_pwrdn_bgz(bool enable);
|
||||
unsigned long dss_get_dpll4_rate(void);
|
||||
int dss_calc_clock_rates(struct dss_clock_info *cinfo);
|
||||
int dss_set_clock_div(struct dss_clock_info *cinfo);
|
||||
int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo);
|
||||
|
||||
typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data);
|
||||
bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data);
|
||||
@ -310,9 +308,6 @@ bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
|
||||
unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
|
||||
int dsi_pll_set_clock_div(struct platform_device *dsidev,
|
||||
struct dsi_clock_info *cinfo);
|
||||
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
|
||||
unsigned long req_pck, struct dsi_clock_info *cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo);
|
||||
int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
|
||||
bool enable_hsdiv);
|
||||
void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
|
||||
@ -343,14 +338,6 @@ static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
|
||||
WARN("%s: DSI not compiled in\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
|
||||
unsigned long req_pck,
|
||||
struct dsi_clock_info *dsi_cinfo,
|
||||
struct dispc_clock_info *dispc_cinfo)
|
||||
{
|
||||
WARN("%s: DSI not compiled in\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int dsi_pll_init(struct platform_device *dsidev,
|
||||
bool enable_hsclk, bool enable_hsdiv)
|
||||
{
|
||||
@ -400,8 +387,6 @@ bool dispc_div_calc(unsigned long dispc,
|
||||
bool dispc_mgr_timings_ok(enum omap_channel channel,
|
||||
const struct omap_video_timings *timings);
|
||||
unsigned long dispc_fclk_rate(void);
|
||||
void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
|
||||
struct dispc_clock_info *cinfo);
|
||||
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
|
||||
struct dispc_clock_info *cinfo);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user