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ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs
This patch removes the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition for ARMv5 and earlier processors. On such processors, the context switch requires a full cache flush. To avoid high interrupt latencies, this patch defers the mm switching to the post-lock switch hook if the interrupts are disabled. Reviewed-by: Will Deacon <will.deacon@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com> Tested-by: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -34,13 +34,4 @@ typedef struct {
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#endif
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/*
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* switch_mm() may do a full cache flush over the context switch,
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* so enable interrupts over the context switch to avoid high
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* latency.
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*/
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#ifndef CONFIG_CPU_HAS_ASID
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#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
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#endif
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#endif
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@ -105,19 +105,40 @@ static inline void finish_arch_post_lock_switch(void)
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#else /* !CONFIG_CPU_HAS_ASID */
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#ifdef CONFIG_MMU
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static inline void check_and_switch_context(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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#ifdef CONFIG_MMU
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if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
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__check_kvm_seq(mm);
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if (irqs_disabled())
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/*
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* cpu_switch_mm() needs to flush the VIVT caches. To avoid
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* high interrupt latencies, defer the call and continue
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* running with the old mm. Since we only support UP systems
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* on non-ASID CPUs, the old mm will remain valid until the
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* finish_arch_post_lock_switch() call.
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*/
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set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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else
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cpu_switch_mm(mm->pgd, mm);
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#endif
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}
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#define init_new_context(tsk,mm) 0
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#define finish_arch_post_lock_switch \
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finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
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struct mm_struct *mm = current->mm;
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cpu_switch_mm(mm->pgd, mm);
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}
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}
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#define finish_arch_post_lock_switch() do { } while (0)
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#endif /* CONFIG_MMU */
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#define init_new_context(tsk,mm) 0
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#endif /* CONFIG_CPU_HAS_ASID */
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